AD5308/AD5318/AD5328
A Version1
Typ
B Version1
Typ
Parameter2
Min
Max
Min
Max
Unit
mA
mA
μs
Conditions/Comments
VDD = 5 V
VDD = 3 V
Coming out of power-down
mode, VDD = 5 V
Short Circuit Current
25.0
1ꢁ.0
2.5
25.0
1ꢁ.0
2.5
Power-Up Time
5.0
5.0
μs
Coming out of power-down
mode, VDD = 3 V
LOGIC INPUTSꢁ
Input Current
VIL, Input Low Voltage
1
0.8
0.8
0.ꢀ
1
0.8
0.8
0.ꢀ
μA
V
V
VDD = 5 V 10%
VDD = 3 V 10%
VDD = 2.5 V
V
VIH, Input High Voltage
1.ꢀ
2.5
1.ꢀ
2.5
V
VDD = 2.5 V to 5.5 V, TTL and
CMOS compatible
Pin Capacitance
POWER REQUIREMENTS
VDD
3.0
3.0
pF
V
5.5
5.5
IDD (Normal Mode)8
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
All DACs in unbuffered
mode, in buffered mode
Extra current is typically x μA
per DAC; x = (5 μA +
VREF/RDAC)/4
1.0
0.ꢀ
1.8
1.5
1.0
0.ꢀ
1.8
1.5
mA
mA
VDD = 2.5 V to 3.ꢁ V
IDD (Power-Down Mode)9
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
0.4
0.12
1
1
0.4
0.12
1
1
μA
μA
VDD = 2.5 V to 3.ꢁ V
1 Temperature range (A, B version): −40°C to +125°C; typical at 25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded unless stated otherwise.
4 Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5 This corresponds to x codes. x = deadband voltage/LSB size.
ꢁ Guaranteed by design and characterization; not production tested.
ꢀ For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
8 Interface inactive. All DACs active. DAC outputs unloaded.
9 All eight DACs powered down.
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. AC Characteristics1
A, B Version2
Parameter3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5308
AD5318
VREF = VDD = 5 V
ꢁ
ꢀ
8
8
9
10
μs
μs
μs
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 To 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
AD5328
Slew Rate
0.ꢀ
12
0.5
0.5
1
3
200
−ꢀ0
V/μs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1 LSB change around major carry
VREF = 2 V 0.1 V p-p, unbuffered mode
VREF = 2.5 V 0.1 V p-p, frequency = 10 kHz
dB
1 Guaranteed by design and characterization; not production tested.
2 Temperature range (A, B version): –40°C to +125°C; typical at 25°C.
3 See the Terminology section.
Rev. F | Page 5 of 28