2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output
12-Bit DAC in an SOT-23
AD5320
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 12-bit DAC
V
DD
GND
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 140 μA @ 5 V
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.7 V to 5.5 V power supply
AD5320
POWER-ON
RESET
REF (+) REF (–)
Guaranteed monotonic by design
Reference derived from power supply
Power-on reset to zero volts
OUTPUT
BUFFER
DAC
REGISTER
V
OUT
12-BIT
DAC
Three power-down functions
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
REGISTER
NETWORK
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
SYNC
SCLK DIN
Figure 1.
GENERAL DESCRIPTION
The AD53201 is a single, 12-bit buffered voltage out digital-to-
analog converter (DAC) that operates from a single 2.7 V to
5.5 V supply consuming 115 μA at 3 V. Its on-chip precision
output amplifier allows rail-to-rail output swing to be achieved.
The AD5320 utilizes a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™ and digital signal
processing (DSP) interface standards.
The AD5320 is one of a family of pin-compatible DACs. The
AD5300 is the 8-bit version and the AD5310 is the 10-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead MSOP packages.
PRODUCT HIGHLIGHTS
1. Available in 6-lead SOT-23 and 8-lead MSOP packages.
2. Low power, single-supply operation. This part operates
from a single 2.7 V to 5.5 V supply and typically consumes
0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery-powered applications.
The reference for AD5320 is derived from the power supply
inputs and thus gives the widest dynamic output range. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to zero volts and remains there until a
valid write takes place to the device. The part contains a power-
down feature that reduces the current consumption of the
device to 200 nA at 5 V and provides software selectable output
loads while in power-down mode. The part is put into power-
down mode over the serial interface.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a slew rate of 1 V/μs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface only powers up during a write cycle.
The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 μW in
power-down mode.
6. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
1 Patent pending; protected by U.S. Patent No. 5684481.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
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