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AD5316ARU-REEL7 PDF预览

AD5316ARU-REEL7

更新时间: 2024-02-05 16:23:29
品牌 Logo 应用领域
亚德诺 - ADI 转换器光电二极管
页数 文件大小 规格书
24页 528K
描述
2.5 V to 5.5 V, 400 μA, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs

AD5316ARU-REEL7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.59最大模拟输出电压:5.499 V
最小模拟输出电压:0.001 V转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm最大线性误差 (EL):0.293%
湿度敏感等级:1位数:10
功能数量:1端子数量:16
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大稳定时间:9 µs
标称安定时间 (tstl):7 µs子类别:Other Converters
最大压摆率:0.9 mA标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

AD5316ARU-REEL7 数据手册

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AD5306/AD5316/AD5326  
TIMING CHARACTERISTICS1  
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
A, B Versions  
ꢀimit at TMIN, TMAX  
Parameter2  
Unit  
Conditions/Comments  
SCL cycle time  
t1  
t2  
t3  
t4  
t5  
2.5  
0.6  
1.3  
0.6  
100  
0.9  
0
0.6  
0.6  
1.3  
300  
0
250  
0
300  
20 + 0.1CB  
20  
μs min  
μs min  
μs min  
μs min  
ns min  
μs max  
μs min  
μs min  
μs min  
μs min  
ns max  
ns min  
ns max  
ns min  
ns max  
ns min  
ns min  
ns min  
pF max  
tHIGH, SCL high time  
tLOW, SCL low time  
tHD,STA, start/repeated start condition hold time  
tSU,DAT, data setup time  
tHD,DAT, data hold time  
3
t6  
t7  
t8  
t9  
t10  
tSU,STA, setup time for repeated start  
tSU,STO, stop condition setup time  
tBUF, bus free time between a stop and a start condition  
tR, rise time of SCL and SDA when receiving  
tR, rise time of SCL and SDA when receiving (CMOS compatible)  
tF, fall time of SDA when transmitting  
tF, fall time of SDA when receiving (CMOS compatible)  
tF, fall time of SCL and SDA when receiving  
tF, fall time of SCL and SDA when transmitting  
LDAC pulse width  
t11  
4
t12  
t13  
400  
400  
SCL rising edge to LDAC rising edge  
4
CB  
Capacitive load for each bus line  
1 See Figure 2.  
2 Guaranteed by design and characterization; not production tested.  
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s  
falling edge.  
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD  
.
START  
CONDITION  
REPEATED START  
CONDITION  
STOP  
CONDITION  
SDA  
SCL  
t9  
t10  
t11  
t4  
t3  
t4  
t2  
t1  
t6  
t5  
t7  
t8  
t12  
1
2
t13  
LDAC  
LDAC  
t12  
NOTES  
1
ASYNCHRONOUS LDAC UPDATE MODE.  
SYNCHRONOUS LDAC UPDATE MODE.  
2
Figure 2. 2-Wire Serial Interface Timing Diagram  
Rev. F | Page 6 of 24  
 
 

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