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AD5314ARMZ-REEL7 PDF预览

AD5314ARMZ-REEL7

更新时间： 2024-01-16 17:38:06
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 357K
描述
2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages

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AD5314ARMZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.25
最大模拟输出电压：5.499 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：S-PDSO-G10
JESD-609代码：e3长度：3 mm
最大线性误差 (EL)：0.3906%湿度敏感等级：1
位数：10功能数量：1
端子数量：10最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP10,.19,20
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.1 mm
最大稳定时间：9 µs标称安定时间 (tstl)：7 µs
子类别：Other Converters最大压摆率：0.9 mA
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3 mm

AD5314ARMZ-REEL7 数据手册

 浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第16页浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第17页浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第18页浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第20页浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第21页浏览型号AD5314ARMZ-REEL7的Datasheet PDF文件第22页 
Data Sheet  
AD5304/AD5314/AD5324  
Opto-Isolated Interface for Process Control Applications  
AD5304  
SCLK  
DIN  
V
V
V
V
A
B
C
D
OUT  
OUT  
OUT  
OUT  
SYNC  
DIN  
The AD5304/AD5314/AD5324 have a versatile 3-wire serial  
inter-face, making them ideal for generating accurate voltages  
in process control and industrial applications. Due to noise,  
safety requirements, or distance, it might be necessary to isolate  
the AD5304/AD5314/AD5324 from the controller. This can  
easily be achieved by using opto-isolators, which provide isolation  
in excess of 3 kV. The actual data rate achieved is limited by the  
type of optocouplers chosen. The serial loading structure of the  
AD5304/AD5314/AD5324 makes them ideally suited for use in  
opto-isolated applications. Figure 42 shows an opto-isolated  
interface to the AD5304 where DIN, SCLK, and SYNC are driven  
from optocouplers. The power supply to the part also needs to  
be isolated. This is done by using a transformer. On the DAC  
side of the transformer, a 5 V regulator provides the 5 V supply  
required for the AD5304.  
V
V
DD  
CC  
SCLK  
1G 74HC139  
ENABLE  
AD5304  
1Y0  
1Y1  
1Y2  
1Y3  
V
V
V
V
A
B
C
D
OUT  
OUT  
OUT  
OUT  
1A  
1B  
SYNC  
DIN  
CODED  
ADDRESS  
SCLK  
DGND  
AD5304  
V
V
V
V
A
B
C
D
OUT  
OUT  
OUT  
OUT  
SYNC  
DIN  
SCLK  
AD5304  
V
V
V
V
A
B
C
D
OUT  
OUT  
OUT  
OUT  
SYNC  
DIN  
SCLK  
5V  
Figure 43. Decoding Multiple AD5304 Devices in a System  
REGULATOR  
10µF  
0.1µF  
POWER  
AD5304/AD5314/AD5324 as a Digitally Programmable  
Window Detector  
V
DD  
DD  
DD  
A digitally programmable upper/lower limit detector using two  
DACs in the AD5304/AD5314/AD5324 is shown in Figure 44.  
The upper and lower limits for the test are loaded to DAC A  
and DAC B, which, in turn, set the limits on the CMP04. If the  
signal at the VIN input is not within the programmed window,  
an LED indicates the fail condition. Similarly, DAC C and DAC D  
can be used for window detection on a second VIN signal.  
5V  
10kΩ  
V
DD  
SCLK  
SCLK  
REFIN  
AD5304  
V
10kΩ  
V
A
B
C
D
OUT  
OUT  
OUT  
OUT  
SYNC  
SYNC  
V
V
V
0.1µF  
10µF  
V
1kΩ  
1kΩ  
IN  
V
FAIL  
PASS  
V
DD  
V
REFIN  
10kΩ  
REF  
V
A
OUT  
1/2  
DIN  
DIN  
AD5304/AD5314/  
AD5324*  
1/2  
CMP04  
GND  
PASS/FAIL  
1/6 74HC05  
SYNC  
SYNC  
DIN  
DIN  
V
B
OUT  
Figure 42. AD5304 in an Opto-Isolated Interface  
SCLK  
SCLK  
GND  
DECODING MULTIPLE AD5304/AD5314/AD5324S  
*ADDITIONAL PINS OMITTED FOR CLARITY.  
SYNC  
The  
pin on the AD5304/AD5314/AD5324 can be used  
Figure 44. Window Detection  
in applications to decode a number of DACs. In this application, all  
the DACs in the system receive the same serial clock and serial  
SYNC  
data, but  
can only be active to one of the devices at any one  
time, allowing access to four channels in this 16-channel system.  
The 74HC139 is used as a 2-to-4-line decoder to address any of the  
DACs in the system. To prevent timing errors, the enable input  
must be brought to its inactive state while the coded address  
inputs are changing state. Figure 43 shows a diagram of a typical  
setup for decoding multiple AD5304 devices in a system.  
Rev. H | Page 19 of 24  
 
 
 
 
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