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AD53032

更新时间： 2024-01-07 03:53:19
品牌 Logo 应用领域
亚德诺 - ADI 驱动器比较器
页数 文件大小 规格书
8页 105K
描述
High Performance Driver/Comparator Active Load on a Single Chip

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AD53032 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP-52针数：52
Reach Compliance Code：unknown风险等级：5.64
Is Samacsys：N差分输出：NO
驱动器位数：1输入特性：DIFFERENTIAL
接口集成电路类型：LINE DRIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-XQFP-G52JESD-609代码：e0
长度：14 mm湿度敏感等级：3
标称负供电电压：-7 V功能数量：1
端子数量：52封装主体材料：UNSPECIFIED
封装代码：HLQFP封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE峰值回流温度（摄氏度）：240
认证状态：COMMERCIAL座面最大高度：1.6 mm
最大供电电压：12.36 V最小供电电压：11.64 V
标称供电电压：12 V表面贴装：YES
端子面层：TIN LEAD端子形式：GULL WING
端子节距：1 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30最大传输延迟：2.1 ns
宽度：14 mmBase Number Matches：1

AD53032 数据手册

 浏览型号AD53032的Datasheet PDF文件第1页浏览型号AD53032的Datasheet PDF文件第2页浏览型号AD53032的Datasheet PDF文件第4页浏览型号AD53032的Datasheet PDF文件第5页浏览型号AD53032的Datasheet PDF文件第6页浏览型号AD53032的Datasheet PDF文件第7页 
AD53032  
Parameter  
Min  
Typ Max  
Units  
Test Conditions  
Delay Change vs. Pulsewidth  
Minimum Pulsewidth  
3 V Swing  
5 V Swing  
Toggle Rate  
<50  
ps  
VL = 0 V, VH = 2 V  
2
3
250  
ns  
ns  
MHz  
VL = 0 V, VH = 3 V, 90% Reached, Measure @ 50%  
VL = 0 V, VH = 5 V, 90% Reached, Measure @ 50%  
VL = 0 V, VH = 5 V, VDUT > 3.0 V p-p  
DYNAMIC PERFORMANCE, INHIBIT  
Delay Time, Active to Inhibit  
Delay Time, Inhibit to Active  
1.5  
1.5  
4.0  
3.5  
±1.0  
2.2  
ns  
ns  
ns  
ns  
Measured at 50%, VH = +2 V, VL = –2 V  
Measured at 50%, VH = +2 V, VL = –2 V  
Delay Time Matching (Z)  
Z = Delay Time Active to Inhibit Test (Above)—  
Delay Time Inhibit to Active Test (Above)  
(Of Worst Two Edges)  
I/O Spike  
Rise, Fall Time, Active to Inhibit  
Rise, Fall Time, Inhibit to Active  
<200  
3.5  
mV, p-p  
ns  
ns  
VH = 0 V, VL = 0 V  
VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)  
VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)  
2.2  
DYNAMIC PERFORMANCE , VTERM  
Delay Time, VH to VTERM  
Delay Time, VL to VTERM  
Delay Time, VTERM to VH and VTERM to VL  
Overshoot and Preshoot  
3.0  
5.0  
4.0  
ns  
ns  
ns  
Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V  
Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V  
Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V  
–3.0 + 75  
35  
+3.0 + 75 % of Step + mV VH/VL, VTERM = (+0.4 V, –0.4 V), (0.0 V, –2.0 V),  
(0.0 V, +7.0 V)  
4.0  
5.5  
VTERM Mode Rise Time  
VTERM Mode Fall Time  
PSRR, DRIVE or TERM Mode  
ns  
ns  
dB  
VL, VH = 0 V, VTERM = –2 V, 20%–80%  
VL, VH = 0 V, VTERM = –2 V, 20%–80%  
VS = VS ± 3%  
Specifications subject to change without notice.  
COMPARATOR SPECIFICATIONS  
(All specifications are at TJ = +85؇C ؎ 5؇C, +VS = +12 V ؎ 3%, –VS = –7 V = ؎3% unless otherwise noted. All temperature coefficients are  
measured at TJ = +75؇C to +95؇C).  
Parameter  
Min  
Typ Max  
Units  
Test Conditions  
DC INPUT CHARACTERISTICS  
Offset Voltage (VOS  
Offset Voltage (Drift)  
HCOMP, LCOMP Bias Current  
Voltage Range (VCM  
)
–25  
25  
50  
mV  
µV/°C  
µA  
CMV = 0 V  
CMV = 0 V  
VIN = 0 V  
–50  
–3  
50  
8.0  
)
V
Differential Voltage (VDIFF  
Gain and Linearity  
)
9.0  
0.05  
V
–0.05  
% FSR  
VIN = –3 V to +8 V  
LATCH ENABLE INPUTS  
Logic “1” Current (IIH  
)
250  
µA  
µA  
LE, LE = –0.8 V  
LE, LE = –1.8 V  
Logic “0” Current (IIL  
)
–250  
DIGITAL OUTPUTS  
Logic “1” Voltage (VOH  
)
–0.98  
V
V
V/ns  
Q or Q, 50 Ω to –2 V  
Q or Q, 50 Ω to –2 V  
Logic “0” Voltage (VOL  
Slew Rate  
)
–1.5  
1
SWITCHING PERFORMANCE  
Propagation Delay  
Input to Output  
0.9  
2.5  
ns  
VIN = 2 V p-p,  
Latch Enable to Output  
Propagation Delay Temperature Coefficient  
Propagation Delay Change with Respect to  
Slew Rate: 0.5 V, 1.0 V, 3.0 V/ns  
Slew Rate: 5.0 V/ns  
Amplitude: 1.0 V, 3.0 V, 5.0 V  
Equivalent Input Rise Time  
Pulsewidth Linearity  
2
2
ns  
ps/°C  
HCOMP = +1 V, LCOMP = +1 V  
<±100  
<±350  
<±200  
450  
<±200  
<25  
ps  
ps  
ps  
ps  
ps  
ns  
VIN = 0 V to 5 V  
VIN = 0 V to 5 V  
VIN = 1.0 V/ns  
VIN = 0 V to 3 V, 3 V/ns  
VIN = 0 V to 3 V, 3 V/ns, PW = 3 ns–8 ns  
Settling to ±8 mV, VIN = 1 V to 0 V  
Settling Time  
Latch Timing  
Input Pulsewidth  
Setup Time  
Hold Time  
<1.5  
<1.0  
<1.0  
ns  
ns  
ns  
Specifications subject to change without notice.  
REV. 0  
–3–  
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