Datasheet > AD5300BRT-REEL7

AD5300BRT-REEL7

更新时间： 2024-02-28 07:40:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	202K
描述
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23

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数据手册

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AD5300BRT-REEL7 数据手册

AD5300

PIN CONFIGURATIONS

MSOP

SOT-23

GND

DIN

SYNC

SCLK

DIN

OUT

AD5300

TOP VIEW

(Not to Scale)

GND

AD5300

TOP VIEW

(Not to Scale)

SCLK

SYNC

OUT

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

SOT-23 MSOP

Pin No. Pin No. Mnemonic

Function

V_OUT

GND

V_DD

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V_DDshould be decoupled

to GND.

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. Data can be transferred at rates up to 30 MHz.

Level Triggered Control Input (Active Low). This is the frame synchronization signal for the

input data. When SYNC goes low, it enables the input shift register and data is transferred in on the

falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless

SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and

the write sequence is ignored by the DAC.

SCLK

SYNC

2, 3

No Connect.

REV. C

–4–

1 2 345 6 7...12

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