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AD53/009-9

更新时间： 2024-02-06 21:05:07
品牌 Logo 应用领域
亚德诺 - ADI GSM
页数 文件大小 规格书
8页 65K
描述
GSM Baseband Processing Chipset

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AD53/009-9 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：LOW PROFILE, PLASTIC, TQFP-80针数：80
Reach Compliance Code：unknown风险等级：5.76
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：14 mm湿度敏感等级：NOT SPECIFIED
功能数量：1端子数量：80
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
座面最大高度：1.6 mm表面贴装：YES
技术：CMOS电信集成电路类型：TELECOM CIRCUIT
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

AD53/009-9 数据手册

 浏览型号AD53/009-9的Datasheet PDF文件第2页浏览型号AD53/009-9的Datasheet PDF文件第3页浏览型号AD53/009-9的Datasheet PDF文件第4页浏览型号AD53/009-9的Datasheet PDF文件第5页浏览型号AD53/009-9的Datasheet PDF文件第7页浏览型号AD53/009-9的Datasheet PDF文件第8页 
AD20msp410  
D igital Audio Inter face (D AI)  
Table I. List of Key Com ponents  
As required by the GSM specifications, a digital audio interface  
is provided to allow certain tests of the audio section during type  
approval. T his interface is provided by the serial bus between  
the ASP and the PLP and two additional control signals from  
the PLP. A fully functional “DAI Box” needed for the FT A  
process may be obtained from Analog Devices upon request.  
Quantity  
D escription  
Specification  
1
1
1
1
1
1
1
ASP1  
ADSP-2178  
ADPLP01  
AD7015  
256K × 16, 150 ns  
128K × 8, 120 ns  
2K × 8  
PLP1  
BBC1  
FLASH-PROM2  
SRAM  
D igital Inter face to the P LP for D ata Ser vices  
A conventional H8 serial port combined with a proprietary  
protocol is used to interface to an external Data T erminal  
Adapter.  
EEPROM3  
Display Driver  
Design Specific  
NOT ES  
1T hese components comprise the AD20msp410 chipset.  
D igital Inter face fr om the P LP to the EEP RO M  
2A size of 4 Mbits is recommended to allow storage of all GSM Layer  
(1, 2, 3) programs as well as a typical user interface (MMI). Larger  
memory can be used to support enhanced user interfaces.  
3Can be omitted if parameters are stored in FLASH memory.  
T he PLP provides separate pins to interface directly to an  
external EEPROM via a serial port. T his EEPROM is typically  
used for storage of calibration or user variable parameters like  
handset identifier (IMEI), language, keypad lock and radio  
calibration parameters. A typical size of the EEPROM is 2K × 8  
bits, but this depends on the individual design of the handset.  
GSM Baseband P r ocessing Key P ar ts List  
T able 1 lists the major hardware components necessary to  
complete the GSM baseband processing subsystem. An example  
Bill Of Material is available from Analog Devices. A full  
reference design is available through Analog Devices/T he  
T echnology Partnership.  
13MHz  
DAI  
VCTCXO  
INTERFACE  
PLP  
BBC  
CAR KIT  
SIM  
INTERFACE  
AUX DAC 2  
(AFC)  
VOICEBAND  
ANALOG I/O  
DAI CONTROL  
SERIAL PORT  
ADDRESS  
DATA  
VOICEBAND  
SERIAL PORT  
SPORT 0  
ASP  
AUX DAC 1  
(AGC)  
POWER  
AMPLIFIER  
ASP  
ADDRESS  
DATA BUS  
INTERFACE  
PSRAM  
CONTROL  
BASEBAND  
SERIAL PORT  
SPORT 1  
RADIO  
IF  
AUX DAC 3  
(AGC)  
DISPLAY  
CONTROL  
AMPLIFIER  
CLOCK  
MODULATOR  
BASEBAND  
ANALOG I/O  
BACKLIGHT  
CONTROL  
DEMODULATOR  
KEYPAD  
INTERFACE  
POWER  
SUBSYSTEM  
POWER  
CONTROL  
KEYPAD  
KEYPAD  
AUX ADC  
EEPROM  
INTERFACE  
SYNTHESIZER  
AND RADIO  
CONTROL  
SYNTHESIZER  
AND RADIO  
CONTROL  
DATA  
DATA  
INTERFACE  
INTERFACE  
Figure 5. System Interfaces  
REV. 0  
–6–  
1...345678

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