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AD5282BRU50 PDF预览

AD5282BRU50

更新时间: 2024-02-10 10:02:38
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器电阻器光电二极管
页数 文件大小 规格书
10页 154K
描述
+15V, I2C Compatible Digital Potentiometers

AD5282BRU50 技术参数

Source Url Status Check Date:2013-05-01 14:56:11.546是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:MO-153AB, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.34其他特性:CAN ALSO OPERATE FROM A SINGLE +5V TO +15V SUPPLY; ALSO REQUIRES A +2.7V TO +5.5V LOGIC SUPPLY
标称带宽:0.15 kHz控制接口:2-WIRE SERIAL
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
湿度敏感等级:1标称负供电电压:-5 V
功能数量:2位置数:256
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:5/15/+-5 V
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:30%最大电阻器端电压:5 V
最小电阻器端电压:-5 V座面最大高度:1.2 mm
子类别:Digital Potentiometers标称供电电压:5 V
表面贴装:YES标称温度系数:30 ppm/ °C
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
标称总电阻:50000 Ω宽度:4.4 mm
Base Number Matches:1

AD5282BRU50 数据手册

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PRELIMINARY TECHNICAL DATA  
AD5280/AD5282  
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,  
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Units  
DYNAMIC CHARACTERISTICS6,9,11  
Bandwidth –3dB  
BW_20K  
BW_50K  
RAB = 20K, Code = 80H  
RAB = 50K, Code = 80H  
650  
142  
69  
0.005  
2
kHz  
kHz  
kHz  
%
BW_200K RAB = 200K, Code = 80H  
THDW  
tS  
Total Harmonic Distortion  
VW Settling Time  
VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz  
VA= VDD, VB=0V, ±1 LSB error band  
µs  
Resistor Noise Voltage  
eN_WB  
RWB = 10K, f = 1KHz  
14  
nVHz  
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)  
SCL Clock Frequency  
fSCL  
t1  
t2  
t3  
t4  
0
400  
0.9  
KHz  
µs  
µs  
µs  
µs  
µs  
µs  
ns  
tBUF Bus free time between STOP & START  
tHD;STA Hold Time (repeated START)  
tLOW Low Period of SCL Clock  
tHIGH High Period of SCL Clock  
tSU;STA Setup Time For START Condition t5  
tHD;DAT Data Hold Time  
tSU;DAT Data Setup Time  
tF Fall Time of both SDA & SCL signals  
tR Rise Time of both SDA & SCL signals t9  
1.3  
0.6  
1.3  
0.6  
0.6  
0
After this period the first clock pulse is generated  
t6  
t7  
t8  
100  
300  
300  
ns  
ns  
tSU;STO Setup time for STOP Condition  
t10  
0.6  
µs  
NOTES:  
1.  
2.  
Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.  
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the  
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3.  
4.  
VAB = VDD, Wiper (VW) = No connect  
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.  
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.  
5.  
6.  
9.  
Resistor terminals A,B,W have no limitations on polarity with respect to each other.  
Guaranteed by design and not subject to production test.  
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value  
result in the minimum overall power consumption.  
10.  
P
is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.  
DISS  
DD DD  
11. All dynamic characteristics use VDD = +5V.  
12. See timing diagram for location of measured values.  
REV PrE 12 MAR 02  
3
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final  
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com  

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