AD5282BRU200-REEL7

更新时间： 2024-01-26 09:58:20

品牌	Logo	应用领域
亚德诺 - ADI		数字电位计
页数	文件大小	规格书
28页	964K
描述
Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer

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AD5ꢀ80/AD5ꢀ8ꢀ

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

Total Harmonic Distortion

THD_W

V_A= 1 V rms, R_AB= 20 kΩ

V_B= 0 V dc, f = 1 kHz

0.01/

V_WSettling Time

Crosstalk

t_S

V_A= 5 V, V_B= 5 V, 1 LSB error band

μs

V_A= V_DD, V_B= 0 V, measure V_W1with

adjacent RDAC making full-scale

code change

nV-s

Analog Crosstalk

CTA

Measure V_W1with V_W2= 5 V p-p @ f =

10 kHz

R_WB= 20 kΩ, f = 1 kHz

−62

Resistor Noise Voltage

e_{N_WB}

nVꢀ√Hz

INTERFACE TIMING CHARACTERISTICS (applies to all parts)^{6, 10, 11}

SCL Clock Frequency

f_SCL

t₁

/00

kHz

μs

1.3

t_BUFBus Free Time Between

Stop and Start

t_HD:STAHold Time (Repeated

Start)

t₂

After this period, the first clock pulse 0.6

is generated

μs

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t₃

t_/

t₅

1.3

0.6

μs

t_SU:STASetup Time for Start

Condition

t_HD:DATData Hold Time

t_SU:DATData Setup Time

t₆

t₇

t₈

0.9

μs

100

t_FFall Time of Both SDA and

SCL Signals

t_RRise Time of Both SDA and

SCL Signals

t_SU:STOSetup Time for STOP

Condition

300

t₉

μs

t₁₀

0.6

¹Typicals represent average readings at 25°C, V_DD= +5 V, V_SS= −5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, wiper (V_W) = no connect.

^/INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

⁷P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁸Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

⁹All dynamic characteristics use V_DD= 5 V.

¹⁰See timing diagram (Figure 3) for location of measured values.

¹¹Standard I²C mode operation is guaranteed by design.

t₂

t₈

t₆

t₉

SCL

SDA

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

t₁

Figure 3. Detailed Timing Diagram

Rev. C | Page / of 28

1 2 345 6 7...28

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