Datasheet > AD5253_12

AD5253_12

更新时间： 2022-04-13 00:30:22

品牌	Logo	应用领域
亚德诺 - ADI		电位器存储
页数	文件大小	规格书
32页	576K
描述
Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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AD5253_12 数据手册

Data Sheet

AD5253/AD5254

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

V_DD= +3 V 10% or +5 V 10%, V_SS= 0 V or V_DD/V_SS= 2.5 V 10%, V_A= V_DD, V_B= 0 V, –40°C < T_A< +105°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

DC CHARACTERISTICS—

RHEOSTAT MODE

Resolution

AD5253/AD5254

6/8

Bits

LSB

Resistor Differential Nonlinearity²R-DNL

R_WB, R_WA= NC, AD5253

R_WB, R_WA= NC, AD5254

R_WB, R_WA= NC, AD5253

R_WB, R_WA= NC, AD5254

T_A= 25°C

−0.75

−1.00

−0.75

−2.5

0.10

0.25

1.0

+0.75

+1.00

+0.75

+2.5

+20

Resistor Nonlinearity²

R-INL

Nominal Resistor Tolerance

Resistance Temperature

Coefficient

ΔR_AB/R_AB

(ΔR_AB/R_AB) × 10⁶/ΔT

−20

650

ppm/°C

Wiper Resistance

R_W

I_W= 1 V/R, V_DD= 5 V

I_W= 1 V/R, V_DD= 3 V

R_AB= 10 kΩ, 50 kΩ

R_AB= 100 kΩ

130

300

Ω

200

0.15

0.05

Channel-Resistance Matching

ΔR_AB1/ΔR_AB2

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

Differential Nonlinearity³

DNL

INL

AD5253

AD5254

AD5253

AD5254

−0.5

−1.0

−0.50

−1.5

0.1

0.3

0.15

0.5

+0.5

+1.0

+0.50

+1.5

LSB

Integral Nonlinearity³

Voltage Divider

Temperature Coefficient

Full-Scale Error

(ΔV_W/V_W) × 10⁶/ΔT Code = half scale

V_WFSECode = full scale, AD5253

V_WZSE

ppm/°C

−1.0

−3

−0.3

−1

0.3

1.2

1.0

3.0

LSB

Code = full scale, AD5254

Code = zero scale, AD5253

Code = zero scale, AD5254

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁴

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

Capacitance⁵A, B

f = 1 kHz, measured to GND,

code = half scale

f = 1 kHz, measured to GND,

code = half scale

Capacitance⁵W

C_W

µA

Common-Mode Leakage Current I_CM

DIGITAL INPUTS AND OUTPUTS

V_A= V_B= V_DD/2

0.01

Input Logic High

V_IH

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or V_DD/V_SS= 2.5 V

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or V_DD/V_SS= 2.5 V

R_PULL-UP= 2.2 kΩ to V_DD= 5 V, V_SS= 0 V

WP = V_DD

2.4

2.1

µA

Input Logic Low

V_IL

0.8

0.6

Output Logic High (SDA)

Output Logic Low (SDA)

WP Leakage Current

A0 Leakage Current

Input Leakage Current

(Other than WP and A0)

Input Capacitance⁵

V_OH

V_OL

I_WP

I_A0

I_I

4.9

0.4

A0 = GND

V_IN= 0 V or V_DD

C_I

Rev. C | Page 5 of 32

1 2 3 456 7 8...32

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