AD5253/AD5254
INTERFACE TIMING CHARACTERISTICS (ALL PARTS)
Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified
with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both
VDD = 3 V and 5 V. When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the
I2C interface at these pins conducts current of about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
Table 3.
Parameter
Symbol
Conditions
Min Typ1 Max Unit
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
400
kHz
µs
µs
1.3
0.6
After this period, the first clock pulse is
generated
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
t3
t4
t5
t6
t7
t8
t9
t10
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
ms
µs
0.9
100
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
EEMEM Data Storing Time
300
300
0.6
tEEMEM_STORE
26
300
EEMEM Data Restoring Time at Power On9
tEEMEM_RESTORE1 VDD rise time dependent. Measure without
decoupling capacitors at VDD and VSS.
EEMEM Data Restoring Time upon Restore
Command or RESET Operation9
tEEMEM_RESTORE2 VDD = 5 V
300
540
µs
µs
EEMEM Data Rewritable Time10
FLASH/EE MEMORY RELIABILITY
Endurance11
tEEMEM_REWRITE
100
kCycles
Years
Data Retention12
100
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ
version at VDD = 2.7V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 in order to minimize IDD_RESTORE current consumption.
7 PDISS is calculated from (IDD × VDD = 5 V).
8 All dynamic characteristics use VDD = 5 V.
9 During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time.
10 Delay time after power-on or RESET before new EEMEM data to be written.
11 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
12 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
Rev. 0 | Page 7 of 28
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