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AD524S

更新时间： 2024-02-15 10:46:10
品牌 Logo 应用领域
亚德诺 - ADI 仪表放大器
页数 文件大小 规格书
16页 395K
描述
Precision Instrumentation Amplifier

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AD524S 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：LCC-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.67Is Samacsys：N
放大器类型：INSTRUMENTATION AMPLIFIER最大平均偏置电流 (IIB)：0.05 µA
标称带宽 (3dB)：1 MHz最小共模抑制比：70 dB
最大输入失调电流 (IIO)：0.035 µA最大输入失调电压：100 µV
JESD-30 代码：S-CQCC-N20JESD-609代码：e0
长度：8.89 mm负供电电压上限：-18 V
标称负供电电压 (Vsup)：-15 V最大非线性：0.01%
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC20,.35SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-15 V认证状态：Not Qualified
座面最大高度：2.54 mm标称压摆率：0.1 V/us
子类别：Instrumentation Amplifier最大压摆率：5 mA
供电电压上限：18 V标称供电电压 (Vsup)：15 V
表面贴装：YES温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED最大电压增益：1000
最小电压增益：1标称电压增益：1000
宽度：8.89 mmBase Number Matches：1

AD524S 数据手册

 浏览型号AD524S的Datasheet PDF文件第7页浏览型号AD524S的Datasheet PDF文件第8页浏览型号AD524S的Datasheet PDF文件第9页浏览型号AD524S的Datasheet PDF文件第11页浏览型号AD524S的Datasheet PDF文件第12页浏览型号AD524S的Datasheet PDF文件第13页 
AD524  
Although instrumentation amplifiers have differential inputs,  
there must be a return path for the bias currents. If this is not  
provided, those currents will charge stray capacitances, causing  
the output to drift uncontrollably or to saturate. Therefore,  
when amplifying “floating” input sources such as transformers  
and thermocouples, as well as ac-coupled sources, there must  
still be a dc path from each input to ground.  
Table I. Output Gain Resistor Values  
Nominal  
Output  
Gain  
R2  
R1, R3  
Gain  
2
5
10  
5 kΩ  
1.05 kΩ  
1 kΩ  
2.26 kΩ  
2.05 kΩ  
4.42 kΩ  
2.02  
5.01  
10.1  
COMMON-MODE REJECTION  
Common-mode rejection is a measure of the change in output  
voltage when both inputs are changed equal amounts. These  
specifications are usually given for a full-range input voltage  
change and a specified source imbalance. “Common-Mode  
Rejection Ratio” (CMRR) is a ratio expression while “Common-  
Mode Rejection” (CMR) is the logarithm of that ratio. For  
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.  
INPUT BIAS CURRENTS  
Input bias currents are those currents necessary to bias the input  
transistors of a dc amplifier. Bias currents are an additional  
source of input error and must be considered in a total error  
budget. The bias currents, when multiplied by the source resis-  
tance, appear as an offset voltage. What is of concern in calculat-  
ing bias current errors is the change in bias current with respect to  
signal voltage and temperature. Input offset current is the differ-  
ence between the two input bias currents. The effect of offset  
current is an input offset voltage whose magnitude is the offset  
current times the source impedance imbalance.  
In an instrumentation amplifier, ac common-mode rejection is  
only as good as the differential phase shift. Degradation of ac  
common-mode rejection is caused by unequal drops across  
differing track resistances and a differential phase shift due to  
varied stray capacitances or cable capacitances. In many appli-  
cations shielded cables are used to minimize noise. This tech-  
nique can create common mode rejection errors unless the  
shield is properly driven. Figures 35 and 36 shows active data  
guards that are configured to improve ac common mode rejec-  
tion by “bootstrapping” the capacitances of the input cabling,  
thus minimizing differential phase shift.  
+V  
S
AD524  
LOAD  
–V  
S
TO POWER  
SUPPLY  
GROUND  
+V  
S
–INPUT  
G = 100  
a. Transformer Coupled  
100⍀  
AD524  
V
RG  
OUT  
2
+V  
S
AD711  
+INPUT  
REFERENCE  
–V  
S
AD524  
Figure 35. Shield Driver, G ≥ 100  
LOAD  
–V  
S
+V  
S
TO POWER  
SUPPLY  
GROUND  
–INPUT  
RG  
AD712  
1
100⍀  
100⍀  
b. Thermocouple  
V
AD524  
OUT  
+V  
S
–V  
S
REFERENCE  
RG  
2
+INPUT  
–V  
S
AD524  
Figure 36. Differential Shield Driver  
GROUNDING  
LOAD  
–V  
S
Many data acquisition components have two or more ground  
pins that are not connected together within the device. These  
grounds must be tied together at one point, usually at the sys-  
tem power-supply ground. Ideally, a single solid ground would  
be desirable. However, since current flows through the ground  
wires and etch stripes of the circuit cards, and since these paths  
have resistance and inductance, hundreds of millivolts can be  
generated between the system ground point and the data  
TO POWER  
SUPPLY  
GROUND  
c. AC Coupled  
Figure 34. Indirect Ground Returns for Bias Currents  
–10–  
REV. E  
1...78910111213...16

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