AD5204/AD5206
TEST CIRCUITS
V
A
A
V
340kΩ
DD
V+ = V ± 10%
DD
V+
W
LOGIC
~
∆V
∆V
MS
PSRR (dB) = 20 log
(
)
B
DD
V
MS
∆V
∆V
%
MS
V
PSS (%/%) =
SS
%
DD
Figure 25. ESD Protection of Digital Pins
Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A
B
DUT
IN
5V
OP279
W
A, B, W
V
V
OUT
OFFSET
GND
OFFSET BIAS
V
SS
Figure 26. ESD Protection of Resistor Terminals
Figure 31. Inverting Programmable Gain Test Circuit
5V
V
OUT
OP279
B
DUT
V+ = V
DD
1LSB = V+/256
V
IN
W
A
W
V+
A
OFFSET
GND
B
V
DUT
OFFSET BIAS
MS
Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
Figure 32. Noninverting Programmable Gain Test Circuit
NO CONNECT
DUT
A
+15V
I
W
W
A
V
IN
W
DUT
V
OP42
OUT
B
B
OFFSET
GND
V
MS
2.5V
–15V
Figure 28. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 33. Gain vs. Frequency Test Circuit
0.1V
R
=
SW
DUT
I
SW
I
MS
CODE = 0x00
I
=
1V/R
W
W
NOMINAL
V+
V
DD
W
DUT
A
W
V
– [V
+ I (R II R )]
AW BW
W2
W1
W
+
V
B
R
=
W
0.1V
V+
I
I
SW
W
–
WHERE V = V
W1 MS
WHEN I = 0
W
B
AND V
= V WHEN I = 1/R
W2
MS
W
V
MS
V
TO V
DD
SS
Figure 29. Wiper Resistance Test Circuit
Figure 34. Incremental On-Resistance Test Circuit
Rev. C | Page 16 of 20