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AD5203AR10 PDF预览

AD5203AR10

更新时间: 2024-02-15 17:03:07
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器电阻器
页数 文件大小 规格书
13页 942K
描述
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, SOIC-24

AD5203AR10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-24
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.66其他特性:REST 3 RESISTOR ARRAY VALUES ARE : 10000OHMS
标称带宽:0.6 kHz控制接口:3-WIRE SERIAL
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.4 mm
功能数量:1位置数:64
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):220
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:30%最大电阻器端电压:5.5 V
最小电阻器端电压:座面最大高度:2.65 mm
标称供电电压:3 V表面贴装:YES
标称温度系数:700 ppm/ °C温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30标称总电阻:10000 Ω
宽度:7.5 mmBase Number Matches:1

AD5203AR10 数据手册

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AD5203  
The data setup and data hold times in the specification table  
determine the data valid time requirements. The last eight bits  
of the data word entered into the serial register are held when  
CS returns high. At the same time CS goes high it gates the  
address decoder which enables one of four positive edge trig-  
gered RDAC latches, see Figure 36 detail.  
All digital inputs are protected with a series input resistor and  
parallel Zener ESD structure shown in Figure 38. Applies to  
digital input pins CS, SDI, SDO, RS, SHDN, CLK.  
1k⍀  
LOGIC  
AD5203  
RDAC 1  
RDAC 2  
CS  
Figure 38. Equivalent ESD Protection Circuit  
ADDR  
DECODE  
RDAC 4  
DYNAMIC CHARACTERISTICS  
CLK  
SDI  
The total harmonic distortion plus noise (THD+N) measures  
0.003% using an offset ground with a rail-to-rail OP279 invert-  
ing op amp test circuit, see Figure 30. Figure 15 plots THD  
versus frequency for both inverting and noninverting amplifier  
topologies. Thermal noise is primarily Johnson noise, typically  
9 nV/Hz for the 10 kversion measured at 1 kHz. For the  
100 kdevice, thermal noise measures 29 nV/Hz. Channel-to-  
channel crosstalk measures less than –65 dB at f = 100 kHz. To  
achieve this isolation, the extra ground pins (AGND) located  
between the potentiometer terminals (A, B, W) must be con-  
nected to circuit ground. The AGND and DGND pins should  
be at the same voltage potential. Any unused potentiometers in  
a package should be connected to ground. Power supply rejec-  
tion is typically –50 dB at 10 kHz (care is needed to minimize  
power supply ripple injection in high accuracy applications).  
SERIAL  
REGISTER  
Figure 36. Equivalent Input Control Logic  
The target RDAC latch is loaded with the last six bits of the  
serial data word completing one RDAC update. Four separate  
8-bit data words must be clocked in to change all four VR  
settings.  
SHDN  
CS  
SDO  
SERIAL  
REGISTER  
Q
D
SDI  
CK  
RS  
CLK  
RS  
Figure 37. Detail, SDO Output Schematic of the AD5203  
REV. 0  
–11–  

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