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AD5160BRJ100 PDF预览

AD5160BRJ100

更新时间： 2024-01-31 23:24:41
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
16页 485K
描述
256-Position SPI-Compatible Digital Potentiometer

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AD5160BRJ100 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：2.90 X 3 MM, PLASTIC, MO-178BA, SOT-23, 8 PIN
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.35Is Samacsys：N
其他特性：IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY标称带宽：0.04 kHz
控制接口：3-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：2.9 mm功能数量：1
位置数：256端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSSOP8,.1封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：220
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：3 V最小电阻器端电压：
座面最大高度：1.45 mm子类别：Digital Potentiometers
标称供电电压：3 V表面贴装：YES
技术：CMOS标称温度系数：45 ppm/ °C
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：100000 Ω宽度：1.6 mm
Base Number Matches：1

AD5160BRJ100 数据手册

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AD5160  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION  
VDD = 5 V ꢀ1%, or 3 V ꢀ1%ꢁ VA = +VDDꢁ VB = 1 Vꢁ –41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.  
Table 1.  
Parameter  
Symbol Conditions  
Min  
Typ1  
Max  
Unit  
DC CHARACTERISTICS  
Rheostat Mode  
Resistor Differential Nonlinearity2  
Resistor Integral Nonlinearity2  
Nominal Resistor Tolerance3  
Resistance Temperature Coefficient  
Wiper Resistance  
R-DNL  
R-INL  
∆RAB  
∆RAB/∆T  
RW  
RWB, VA = no connect  
RWB, VA = no connect  
TA = 25°C  
−1.5 ±±.1  
+1.5  
+2±  
12±  
LSB  
LSB  
%
ppm/°C  
Ω
−4  
±±.ꢀ5 +4  
−2±  
VAB = VDD, wiper = no connect  
45  
5±  
Potentiometer Divider Mode  
Specifications apply to all VRs  
Resolution  
N
8
Bits  
Differential Nonlinearity4  
Integral Nonlinearity4  
Voltage Divider Temperature Coefficient  
Full-Scale Error  
DNL  
INL  
∆VW/∆T  
VWFSE  
VWZSE  
−1.5 ±±.1  
−1.5 ±±.6  
15  
+1.5  
+1.5  
LSB  
LSB  
ppm/°C  
LSB  
LSB  
Code = ±x8±  
Code = ±xFF  
Code = ±x±±  
−6  
±
−2.5  
+2  
±
+6  
Zero-Scale Error  
RESISTOR TERMINALS  
Voltage Range5  
Capacitance A, Capacitance B6  
Capacitance W6  
Common-Mode Leakage  
DIGITAL INPUTS  
VA, VB, VW  
CA,B  
CW  
GND  
VDD  
V
f = 1 MHz, measured to GND, code = ±x8±  
f = 1 MHz, measured to GND, code = ±x8±  
VA = VB = VDD/2  
45  
6±  
1
pF  
pF  
nA  
ICM  
Input Logic High  
Input Logic Low  
Input Logic High  
Input Logic Low  
Input Current  
Input Capacitance6  
VIH  
VIL  
VIH  
VIL  
IIL  
2.4  
2.1  
V
V
V
V
μA  
pF  
±.8  
VDD = 3 V  
VDD = 3 V  
VIN = ± V or 5 V  
±.6  
±1  
CIL  
5
3
POWER SUPPLIES  
Power Supply Range  
Supply Current  
Power Dissipationꢀ  
Power Supply Sensitivity  
DYNAMIC CHARACTERISTICS6, 8  
Bandwidth –3 dB  
Total Harmonic Distortion  
VW Settling Time  
VDD RANGE  
IDD  
PDISS  
2.ꢀ  
5.5  
8
±.2  
V
μA  
mW  
VIH = 5 V or VIL = ± V  
VIH = 5 V or VIL = ± V, VDD = 5 V  
∆VDD = +5 V ± 1±%, code = midscale  
PSS  
±±.±2 ±±.±5 %/%  
BW_5K  
THDW  
tS  
RAB = 5 kΩ, code = ±x8±  
VA = 1 V rms, VB = ± V, f = 1 kHz  
VA = 5 V, VB = ± V, ±1 LSB error band  
RWB = 2.5 kΩ  
1.2  
±.±5  
1
MHz  
%
μs  
Resistor Noise Voltage Density  
eN_WB  
6
nV/√Hz  
1 Typical specifications represent average readings at +25°C and VDD = 5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =  
± V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
8 All dynamic characteristics use VDD = 5 V.  
Rev. B | Page 3 of 16  
 
 
 
 
 
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