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AD5061YRJZ-1500RL7 PDF预览

AD5061YRJZ-1500RL7

更新时间: 2024-01-22 05:08:57
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 输入元件光电二极管转换器
页数 文件大小 规格书
21页 1730K
描述
SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN

AD5061YRJZ-1500RL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:LSSOP,针数:8
Reach Compliance Code:unknown风险等级:5.73
最大模拟输出电压:4.096 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:2.9 mm
最大线性误差 (EL):0.0061%湿度敏感等级:1
位数:16功能数量:1
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.45 mm
标称安定时间 (tstl):4 µs标称供电电压:3 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.6 mm
Base Number Matches:1

AD5061YRJZ-1500RL7 数据手册

 浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第5页浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第6页浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第7页浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第9页浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第10页浏览型号AD5061YRJZ-1500RL7的Datasheet PDF文件第11页 
AD5061  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
8
7
6
5
DIN  
SCLK  
AD5061  
V
TOP VIEW  
DD  
SYNC  
(Not to Scale)  
DACGND  
V
REF  
V
AGND  
OUT  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
DIN  
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the  
serial clock input.  
2
3
4
5
6
7
VDD  
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.  
Reference Voltage Input.  
Analog Output Voltage from DAC.  
Ground Reference Point for Analog Circuitry.  
Ground Input to the DAC.  
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC  
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.  
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the  
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.  
VREF  
VOUT  
AGND  
DACGND  
SYNC  
8
SCLK  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can  
be transferred at rates up to 30 MHz.  
Rev. A | Page 7 of 20  
 

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