AD2S99
CONNECTING THE AD2S99 OSCILLATOR
20
18
Refer to Figure 1. Positive supply voltage VDD should be con-
nected to Pin 12 and negative supply voltage VSS should be con-
nected to both Pins 19 and 20. Reversal of these power supplies will
destroy the device. The appropriate voltage level for the power
supplies is ±5 V dc ± 5%. Both VSS Pins (19 and 20) must be
connected together, and Digital Ground (Pin 6) must be con-
nected to Analog Ground (Pin 16) locally at the AD2S99.
16
14
12
10
8
6
VSS
4.7µF
0.1µF
4
2
0
3
2
20 19
1
RESOLVER
0
4
8
12
ADDITIONAL RESISTANCE – kΩ
RESISTOR PULLUP TO VDD FROM FBIAS
16
20
24
28
EXC
NC
4
5
6
7
8
18
17
16
15
14
REF
SIN
SIN
EXC
DGND
COS
AGND
Figure 2. Typical Added Resistance Value
AD2S99
NC
NC
COS
AD2S99 OSCILLATOR OUTPUT STAGE
NC
The output of the AD2S99 oscillator consists of two sinusoidal
signals, EXC, and EXC. EXC is 180° phase advanced with re-
spect to EXC. The excitation winding of a transducer should be
connected across EXC (Pin 17) and EXC (Pin 18).
9
10 11 12 13
.
.
.
RX
*
100nF
TO AD2S80/
AD2S90 REF INPUT
50kΩ
100kΩ
With low impedance transducers, it may be necessary to in-
crease the output current drive of the AD2S99. In such an in-
stance, an external buffer amplifier can be used to provide gain
(as needed), and additional current drive for the excitation out-
put (either EXC or EXC) of the AD2S99, providing a single
ended drive to the transducer. Refer to Figures 6, 7 and 8 for
sample buffer configurations.
4.7µF
0.1µF
SEL2 = GND ]
–5kHz MODE
VDD
SEL1 = VSS
]
INCREASE RX TO LOWER
OUTPUT FREQUENCY
(SEE GRAPH)
NC = NO CONNECT
*R
X IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES.
FIXED FREQUENCIES ONLY REQUIRE A LINK.
The amplitude modulated SIN and COS output signals from a re-
solver should be connected as feedback signals to the AD2S99.
The SYNREF output compensates for any primary to secondary
phase errors in the resolver. These errors can degrade the accuracy
of a Resolver-to-Digital Converter (R/D Converter).
Figure 1. Typical Configuration
It is recommended that decoupling capacitors are connected in
parallel between VDD and Analog Ground and VSS and Analog
Ground in close proximity to the AD2S99. The recommended
values for the decoupling capacitors are 100 nF (ceramic) and
4.7 µF (tantalum). When multiple AD2S99s are used, separate
decoupling capacitors should be used for each AD2S99.
SIN, from the resolver, should be connected to the AD2S99 SIN
input and COS should be connected to the AD2S99 COS input.
The SIN Lo, COS Lo (resolver signal returns) should be con-
nected to AGND and the R/D Converter as applicable.
FREQUENCY ADJUSTMENT
The output frequency of the AD2S99 is programmable to four
standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and
SEL2 pins. The output can also be adjusted to provide interme-
diate frequencies by connecting a resistor from the FBIAS pin to
the positive supply VDD. The FBIAS pin is connected directly to
VDD during normal operation. A graph showing the typical
added resistance values for various intermediate frequencies is
provided in Figure 2. The procedure for obtaining an intermedi-
ate frequency is:
The synthesized reference (SYNREF) from the AD2S99 should
be connected to the reference input pin of the R/D Converter.
The SYNREF signal is a square wave at the oscillator frequency
of amplitude ±3 V p-p and is phase coherent with the SIN and
COS inputs. If this signal is used to drive the reference input of
the AD2S90 R/D Converter, a coupling capacitor and resistor to
GND must be connected between the SYNREF output of the
AD2S99 and the REF input of the R/D Converter (see Figure
3). Please read the appropriate R/D Converter data sheets for
further clarification.
1. Set the output frequency via the SEL1, SEL2 pins to the fre-
quency immediately above the required intermediate frequency.
LOSS OF SIGNAL
2. Connect the frequency adjust pin FBIAS to VDD via an exter-
nal resistor.
During normal operation when both the SIN and COS signals
on the resolver secondary windings are connected to the
AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a
Logic Lo (<0.7 V). If both the SIN and COS signals on the re-
solver secondary windings fall below the LOS threshold level of
the AD2S99, the LOS pin of the AD2S99 will pull up to a
Logic Hi (VDD) level.
For example: to obtain an output frequency of 8 kHz, set the
nominal output frequency to 10 kHz by connecting SEL1 to
GND and SEL2 to VSS. Connect FBIAS to VDD via a 6 kΩ
resistor (refer to Figure 2).
–4–
REV. B
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