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AD1981BJST-REEL

更新时间： 2024-01-20 12:50:21
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器
页数 文件大小 规格书
28页 270K
描述
AC ’97 SoundMAX Codec

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AD1981BJST-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP48,.35SQ,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.6
其他特性：IT CAN REQUIRES 2.97V TO 3.63V SUPPLY商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3,5 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Other Consumer ICs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

AD1981BJST-REEL 数据手册

 浏览型号AD1981BJST-REEL的Datasheet PDF文件第7页浏览型号AD1981BJST-REEL的Datasheet PDF文件第8页浏览型号AD1981BJST-REEL的Datasheet PDF文件第9页浏览型号AD1981BJST-REEL的Datasheet PDF文件第11页浏览型号AD1981BJST-REEL的Datasheet PDF文件第12页浏览型号AD1981BJST-REEL的Datasheet PDF文件第13页 
AD1981B  
Reset Register (Index 00h)  
Reg  
No.  
Name  
D15  
D14  
D13 D12  
SE3 SE2  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
00h  
Reset  
X
SE4  
SE1  
SE0  
ID9  
ID8 ID7  
ID6  
ID5  
ID4  
ID3  
ID2  
ID1 ID0 0090h  
NOTES  
X in the above table is a wild card and has no effect on the value.  
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).  
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.  
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:  
Bit  
Function  
AD1981B  
ID0  
ID1  
ID2  
ID3  
ID4  
ID5  
ID6  
ID7  
ID8  
ID9  
Dedicated Mic PCM In Channel  
Modem Line Codec Support  
Bass and Treble Control  
Simulated Stereo (Mono to Stereo)  
Headphone Out Support  
Loudness (Bass Boost) Support  
18-Bit DAC Resolution  
20-Bit DAC Resolution  
18-Bit ADC Resolution  
20-Bit ADC Resolution  
0
0
0
0
1
0
0
1
0
0
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).  
Master Volume Register (Index 02h)  
Reg  
No.  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
D6 D5 D4  
D3  
D2  
D1  
D0  
Default  
02h  
Master  
MM LMV4 LMV3 LMV2 LMV1 LMV0 RM*  
X
X
X
X
RMV4 RMV3 RMV2 RMV1 RMV0 8000h  
Volume  
* For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right  
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.  
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each  
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume  
registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically  
set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.  
RMV[4:0]  
RM  
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from  
0 dB to a maximum attenuation of 46.5 dB.  
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately  
from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.  
LMV[4:0]  
MM  
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from  
0 dB to a maximum attenuation of 46.5 dB.  
Master Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT  
bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.  
REV. B  
–10–  
1...78910111213...28

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