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AD1981B PDF预览

AD1981B

更新时间: 2024-01-27 01:21:50
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器
页数 文件大小 规格书
28页 270K
描述
AC ’97 SoundMAX Codec

AD1981B 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.6
其他特性:IT CAN REQUIRES 2.97V TO 3.63V SUPPLY商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
功能数量:1端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3,5 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
Base Number Matches:1

AD1981B 数据手册

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AD1981B  
MADST  
Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels).  
0 = Mixer ADC not ready.  
1 = Mixer ADC ready.  
2CMIC  
2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that  
use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h.  
0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector’s left and right MIC channels as well  
as to the mixer (reset default).  
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s  
right MIC channel. Note that in this mode, the MS bit should be set low and MIC1 can still be enabled into the mixer.  
MADPD  
FMXE  
Mixer ADC Power Down. Controls power down for mixer digitizing ADC.  
0 = Mixer ADC is powered on (default).  
1 = Mixer ADC is powered down.  
Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches.  
0 = Front DAC outputs are allowed to sum into the mixer (reset default).  
1 = Front DAC outputs are muted into the mixer (blocked).  
DAM  
Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.  
LODIS  
LINE_OUT Disable. Disables the LINE_OUT pins (L/R), placing them into High Z mode so that the assigned  
output audio jack can be shared for input function (or other function).  
0 = LINE_OUT pins have normal audio drive capability (reset default).  
1 = LINE_OUT pins are placed into High Z mode.  
MSPLT  
DACZ  
Mute Split. Allows separate mute control bits for Master, Headphone, LINE_IN, CD, AUX, and PCM volume control  
registers as well as record gain register.  
0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default).  
1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute.  
DAC Zero-Fill. Determines DAC data fill under starved conditions.  
0 = DAC data is repeated when DACs are starved for data (reset default).  
1 = DAC is zero-filled when DACs are starved for data.  
Vendor ID Register (Index 7Ch–7Eh)  
Reg  
No. Name  
D15 D14 D13  
F6 F5  
D12 D11 D10 D9 D8  
F4 F3 F2 F1 F0  
D7  
D6  
D5  
D4 D3 D2 D1 D0 Default  
7Ch Vendor ID1 F7  
S7  
S6  
S5  
S4  
S3  
S2 S1 S0 4144h  
S[7:0] This register is ASCII encoded to A.  
F[7:0] This register is ASCII encoded to D.  
Reg  
No. Name  
D15 D14 D13 D12 D11 D10 D9 D8 D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h  
T[7:0] This register is ASCII encoded to S.  
REV[7:0] Vendor specific revision number: The AD1981B assigns 74h to this field.  
Table IX. Codec ID and External Clock Selection Table  
ID1  
ID0  
Codec ID  
Codec Clocking Source  
1
1
0
0
1
0
1
0
(00) Primary  
(01) Secondary  
(00) Primary  
(00) Primary  
24.576 MHz  
12.288 MHz  
48.000 MHz  
14.31818 MHz  
(Local Xtal or External into XTL_IN)  
(External into BIT_CLK)  
(External into XTL_IN)  
(External into XTL_IN)  
Note that internally, the ID pins have weak pull-ups and are inverted.  
REV. B  
–26–  

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