AD1959–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature
Input Clock
Input Signal
25°C
12.288 MHz
996.11 Hz
–0.5 dB Full Scale
48 kHz
Input Sample Rate
Measurement Bandwidth
Word Width
20 Hz to 20 kHz
20 Bits
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
100 pF
47 kΩ
3.5 V
0.8 V
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
24
Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
105
108
dB
dB
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Analog Outputs
105
108
–94
dB
dB
dB
101
–91
125
27
MHz
33.8688
12.288
22.5792
85
MHz
MHz
MHz
ps rms
Single-Ended Output Range ( Full Scale)
Output Capacitance at Each Output Pin
VREF (FILTR)
3.17
V p-p
pF
V
2
2.44
+5
2.34
–5
2.39
2.0
Gain Error
%
Interchannel Gain Mismatch
Gain Drift
DC Offset
Out-of-Band Energy (0.5 × fS to 100 kHz)
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
De-Emphasis Gain Error
–0.15
0.015
150
–5
+0.15
250
+15
–90
dB
ppm/°C
mV
dB
dB
Degrees
–25
–120
0.1
0.1
dB
NOTES
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (–40°C to +105°C )
Min
Typ
Max
Unit
Input Voltage HI (VIH) Except XIN
Input Voltage HI (VIH) XIN
2.2
2.7
V
V
Input Voltage LO (VIL)
0.8
10
10
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA Except XOUT
Low Level Output Voltage (VOL) IOL = 1 mA XOUT
Input Capacitance
µA
µA
V
V
V
2.0
0.4
1.2
20
pF
Specifications subject to change without notice.
–2–
REV. 0