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AD1883JCPZ-RL

更新时间： 2024-02-22 06:15:00

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
20页	281K
描述
High Definition Audio SoundMAX Codec

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技术参数
数据手册

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AD1883JCPZ-RL 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
其他特性：	IT ALSO REQUIRES 2.97V TO 3.63V DIGITAL SUPPLY	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-XQCC-N48	长度：	7 mm
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.46 V	最小供电电压 (Vsup)：	3.13 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	7 mm
Base Number Matches：	1

AD1883JCPZ-RL 数据手册

AD1883

Parameter

Min

Typ

Max

Unit

POWER SUPPLY

Analog (AV_DD) 3.3 V ± 5%

Power Supply Range

Power Dissipation

3.13

3.30

75.9

3.46

Supply Current

Digital (DV_DD) 3.3 V ± 10%

Power Supply Range

Power Dissipation

2.97

3.30

141.9

3.63

Supply Current

Digital (DV_CORE) 1.7 through 1.9 V ± 10%

Power Supply Range

Power Dissipation

1.615

2.97

1.70

1.995

3.63

Supply Current

Digital I/O (DV_IO) 3.3 V ± 10%

Power Supply Range

Power Dissipation

3.30

3.3

Supply Current

Digital I/O (DV_IO) 1.5 V ± 5.5%

Power Supply Range

Power Dissipation

1.418

1.50

0.08

0.05

1.583

Supply Current

Power Supply Rejection (Reference to f_S100 mV p-p Signal @ 1 kHz)¹

¹Guaranteed but not tested.

HD AUDIO LINK SPECIFICATION

High definition audio signals comply with the High Definition

Audio Specification. Please refer to these specifications at

www.intel.com/standards/hdaudio.

POWER-DOWN STATES

Table 4. Power-Down States

Parameter

ID_VDDTyp (1.7 V)

ID_VDDTyp (3.3 V)

IA_VDDTyp

Unit

Function Node in D0, All Nodes Active

Function Node in D3

7.5

15.75

7.5

Function Node in D3¹

Codec in RESET

Individual Block Power Savings

DAC Pair Powered Down Saves (Each)

ADC Pair Powered Down Saves (Each)

Mixer Power Control (and Associated Amps) Saves

DM_CLK Powered Down Saves²

MIC_BIAS Powered Down Saves³

4.5

0.1

¹Maximum power saving mode; Register 0x31FD, Bit 4.

²Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V A_VDD.

³Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The

0 V and high-Z states remain unaffected by the MIC_BIAS power state.

Rev. 0

Page 7 of 20

April 2008

1...4 5 678 9 10...20

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