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AD1868R-J

更新时间: 2024-01-10 03:27:31
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管信息通信管理
页数 文件大小 规格书
12页 249K
描述
Single Supply Dual 18-Bit Audio DAC

AD1868R-J 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
最大模拟输出电压:1 V最小模拟输出电压:-1 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.3 mm
湿度敏感等级:1位数:18
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.65 mm最大压摆率:14 mA
标称供电电压:5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.5 mm
Base Number Matches:1

AD1868R-J 数据手册

 浏览型号AD1868R-J的Datasheet PDF文件第3页浏览型号AD1868R-J的Datasheet PDF文件第4页浏览型号AD1868R-J的Datasheet PDF文件第5页浏览型号AD1868R-J的Datasheet PDF文件第7页浏览型号AD1868R-J的Datasheet PDF文件第8页浏览型号AD1868R-J的Datasheet PDF文件第9页 
AD1868  
Figure 1 illustrates the typical T HD+N versus frequency perfor-  
mance of the AD1868. It is evident that the T HD+N perfor-  
mance of the AD1868 remains stable at all three levels through  
a wide range of frequencies. A load impedance of at least 2 kis  
recommended for best T HD+N performance.  
+
5V  
AD1868  
V
L
O
16  
15  
14  
13  
12  
11  
10  
V
1
2
V
L
B
L
V
LL  
DL  
S
V
L
O
3
4
Analog Devices tests and grades all AD1868s on the basis of  
T HD+N performance. During the distortion test, a high speed  
digital pattern generator transmits digital data to each channel  
of the device under test. Eighteen-bit data is latched into the  
DAC at 352.8 kHz (8× FS). T he test waveform is a 990.5 Hz  
sine wave with 0 dB, –20 dB, and –60 dB amplitudes. A 4096-  
point FFT calculates total harmonic distortion + noise,  
signal-to-noise ratio, and D-range. No deglitchers or external  
adjustments are used.  
NRL  
CK  
DR  
5
6
7
8
AGND  
LR  
NRR  
V
R
O
DGND  
+
5V  
V
S
9
V
R
B
V
R
O
D IGITAL CIRCUIT CO NSID ERATIO NS  
INP UT D ATA  
Figure 8b. Circuitry Using Voltage Biases  
T he AD1868 eliminates the need for “False Ground” circuitry.  
VBR and VBL generate the required bias voltages previously  
generated by the “False Ground.” As shown in Figure 8b, VBR  
and VBL may be used as the reference point in each output  
channel. T his permits a dc-coupled output signal path. T his  
eliminates ac-coupling capacitors and improves low frequency  
performance. It should be noted that these bias outputs have  
relatively high output impedance and will not drive output  
currents larger than 100 µA without degrading the specified  
performance.  
T he AD1868 digital input port employs five signals: Data Left  
(DL), Data Right (DR), Latch Left (LL), Latch Right (LR) and  
Clock (CLK). DL and DR are the serial inputs for the left and  
right DACs, respectively. Input data bits are clocked into the in-  
put register on the rising edge of CLK. T he falling edges of LL  
and LR cause the last 18 bits which were clocked into the serial  
registers to be shifted into the DACs, thereby updating the re-  
spective DAC outputs. For systems using only a single latch sig-  
nal, LL and LR may be connected together. For systems using  
only one DAT A signal, DR and DL may be connected together.  
Data is transmitted to the AD1868 in a bit stream composed of  
18-bit words with a serial, twos complement, MSB first format.  
Left and right channels share the Clock (CLK) signal.  
D ISTO RTIO N P ERFO RMANCE AND TESTING  
T he T HD+N figure of an audio DAC represents the amount of  
undesirable signal produced during reconstruction and playback  
of an audio waveform. T herefore, the T HD+N specification  
provides a direct method to classify and choose an audio DAC  
for a desired level of performance.  
Figure 9 illustrates the general signal requirements for data  
transfer for the AD1868.  
CLK  
DL  
DR  
MSB  
MSB  
LSB  
LSB  
LL  
LR  
Figure 9. Control Signals  
REV. A  
–6–  

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