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AD1868R-J

更新时间: 2024-02-19 16:07:00
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管信息通信管理
页数 文件大小 规格书
12页 249K
描述
Single Supply Dual 18-Bit Audio DAC

AD1868R-J 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
最大模拟输出电压:1 V最小模拟输出电压:-1 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.3 mm
湿度敏感等级:1位数:18
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.65 mm最大压摆率:14 mA
标称供电电压:5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.5 mm
Base Number Matches:1

AD1868R-J 数据手册

 浏览型号AD1868R-J的Datasheet PDF文件第2页浏览型号AD1868R-J的Datasheet PDF文件第3页浏览型号AD1868R-J的Datasheet PDF文件第4页浏览型号AD1868R-J的Datasheet PDF文件第6页浏览型号AD1868R-J的Datasheet PDF文件第7页浏览型号AD1868R-J的Datasheet PDF文件第8页 
AD1868  
DAC, the AD1868 can continue to function at supply voltages  
as low as 3.5 V. Because of its unique design, the power require-  
ments of the AD1868 diminish as the battery voltage drops, fur-  
ther extending the operating time of the system.  
AD1868  
18-BIT  
DAC  
V
V
V
L
L
L
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
B
+
18-BIT  
SERIAL  
REGISTER  
LL  
DL  
S
POWER  
SUPPLY  
V
O
V
REF  
NRL  
AD1868  
CK  
V
V
V
L
16  
B
1
2
L
0.1µF  
V
AGND  
NRR  
LL  
DL  
CK  
DR  
15  
14  
S
18-BIT  
SERIAL  
REGISTER  
L
O
3
4
4.7µF  
4.7µF  
V
REF  
LR  
NRL 13  
0.1µF  
12  
5
6
DR  
AGND  
+
V
R
DGND  
O
18-BIT  
DAC  
NRR 11  
LR  
V
R
10  
9
DGND  
O
7
8
V
V
R
S
B
V
S
V
R
B
Functional Block Diagram  
Figure 7. Recom m ended Circuit Schem atic  
ANALO G CIRCUIT CO NSID ERATIO NS  
GRO UND ING RECO MMEND ATIO NS  
NO ISE RED UCTIO N CAP ACITO RS  
T he AD1868 has two ground pins, designated as AGND (Pin  
12) and DGND (Pin 7). T he analog ground, AGND, serves as  
the “high quality” reference ground for analog signals and as a  
return path for the supply current from the analog portion of the  
device. T he system analog common should be located as close  
as possible to Pin 12 to minimize any voltage drop which may  
develop between these two points, although the internal circuit  
is designed to minimize signal dependence of the analog return  
current.  
T he AD1868 has two noise reduction pins designated as NRL  
(Pin 13) and NRR (Pin 11). It is recommended that external  
noise reduction capacitors be connected from these pins to  
AGND to reduce the output noise contributed by the voltage  
reference circuitry. As shown in Figure 7, each of these pins  
should be bypassed to AGND with a 4.7 µF or larger capacitor.  
T he connections between the capacitors, package pins and  
AGND should be as short as possible to achieve the lowest  
noise.  
T he digital ground, DGND, returns ground current from the  
digital logic portion of the device. T his pin should be connected  
to the digital common node in the system. As shown in Figure  
7, the analog and digital grounds should be joined at one point  
in the system. When these two grounds are remotely connected  
such as at the power supply ground, care should be taken to  
minimize the voltage difference between the DGND and AGND  
pins in order to ensure the specified performance.  
USING VBL AND VBR  
T he AD1868 has two bias voltage reference pins, designated as  
VBR (Pin 8) and VBL (Pin 16). T hese pins supply a dc reference  
voltage equal to the center of the output voltage swing. T hese  
bias voltages replace “False Ground” networks previously required  
in single-supply audio systems. At the same time, they allow dc-  
coupled systems, improving audio performance.  
Figure 8a illustrates the traditional approach used to generate  
False Ground voltages in single-supply audio systems. T his cir-  
cuit requires additional power and circuit board space.  
P O WER SUP P LIES AND D ECO UP LING  
T he AD1868 has three power supply input pins. VS (Pins 9 and  
15) provides the supply voltages which operate the analog por-  
tion of the device including the 18-bit DACs, the voltage refer-  
ences, and the output amplifiers. T he VS supplies are designed  
to operate with a +5 V supply. T hese pins should be decoupled  
to analog common using a 0.1 µF capacitor. Good engineering  
practice suggests that the bypass capacitors be placed as close as  
possible to the package pins. T his minimizes the inherent induc-  
tive effects of printed circuit board traces.  
–V  
+V  
S
1
2
3
16  
16-BIT  
LATCH  
S
16-BIT  
DAC  
DGND  
15 TRIM  
MSB  
+V  
L
SERIAL  
INPUT  
14  
ADJ  
REGISTER  
I
I
NC  
CLK  
LE  
4
5
6
7
13  
12  
OUT  
OUT  
VL (Pin 1) operates the digital portions of the chip including the  
input shift registers and the input latching circuitry. VL is also  
designed to operate with a +5 V supply. T his pin should be by-  
passed to digital common using a 0.1 µF capacitor, again placed  
as close as possible to the package pin. Figure 7 illustrates the cor-  
rect connection of the digital and analog supply bypass capacitors.  
AGND  
CONTROL  
LOGIC  
11 SJ  
R
DATA  
10  
9
F
V
NC  
8
OUT  
An important feature of the AD1868 audio DAC is its ability to  
operate at reduced power supply voltages. T his feature is very  
important in portable battery operated systems. As the batteries  
discharge, the supply voltage drops. Unlike any other audio  
AD1851  
NC = NO CONNECT  
Figure 8a. Schem atic Using False Ground  
REV. A  
–5–  

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