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AD9886KS-100

更新时间： 2024-01-14 03:48:43
品牌 Logo 应用领域
亚德诺 - ADI 显示器消费电路商用集成电路
页数 文件大小 规格书
32页 247K
描述
Analog Interface for Flat Panel Displays

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AD9886KS-100 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：PLASTIC, MQFP-160针数：160
Reach Compliance Code：unknown风险等级：5.72
其他特性：IT ALSO REQUIRES 2.2V TO 3.6V DIGITAL SUPPLY商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQFP-G160JESD-609代码：e0
长度：28 mm湿度敏感等级：NOT SPECIFIED
功能数量：1端子数量：160
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
座面最大高度：4.07 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

AD9886KS-100 数据手册

 浏览型号AD9886KS-100的Datasheet PDF文件第2页浏览型号AD9886KS-100的Datasheet PDF文件第3页浏览型号AD9886KS-100的Datasheet PDF文件第4页浏览型号AD9886KS-100的Datasheet PDF文件第5页浏览型号AD9886KS-100的Datasheet PDF文件第6页浏览型号AD9886KS-100的Datasheet PDF文件第7页 
Analog Interface for  
Flat Panel Displays  
a
AD9886  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Analog Interface  
140 MSPS Maximum Conversion Rate  
330 MHz Analog Bandwidth  
0.5 V to 1.0 V Analog Input Range  
500 ps p-p PLL Clock Jitter at 140 MSPS  
3.3 V Power Supply  
ANALOG INTERFACE  
CLAMP  
AD9886  
8
8
R
R
OUTA  
8
8
8
R
G
B
A/D  
A/D  
A/D  
IN  
IN  
IN  
OUTB  
Full Sync Processing  
Midscale Clamp for YUV Applications  
8
8
G
G
OUTA  
CLAMP  
CLAMP  
OUTB  
8
8
B
B
OUTA  
GENERAL DESCRIPTION  
OUTB  
The AD9886 is a complete 8-bit 140 MSPS monolithic analog  
interface optimized for capturing RGB graphics signals from  
personal computers and workstations. Its 140 MSPS encode  
rate capability and full-power analog bandwidth of 330 MHz  
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).  
2
DATACK  
HSYNC  
COAST  
CLAMP  
CKINV  
CKEXT  
FILT  
HSOUT  
VSOUT  
SYNC  
PROCESSING  
AND CLOCK  
GENERATION  
For ease of design and to minimize cost, the AD9886 is a fully  
integrated interface solution for FPDs. The AD9886 includes a  
140 MHz triple ADC with internal 1.25 V reference, PLL to  
generate a pixel clock from an HSYNC, and programmable  
gain, offset, and clamp control. The user provides only a 3.3 V  
power supply, analog input, and an HSYNC signal. Three-state  
CMOS outputs may be powered from 2.5 V to 3.3 V.  
SOGOUT  
REFOUT  
REFIN  
REF  
SCL  
SDA  
SERIAL REGISTER AND  
POWER MANAGEMENT  
A
1
0
The AD9886’s on-chip PLL generates a pixel clock from an  
HSYNC. Pixel clock output frequencies range from 12 MHz to  
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.  
When the COAST signal is presented, the PLL maintains its  
output frequency in the absence of HSYNC. A sampling phase  
adjustment is provided. Data, HSYNC and Clock output phase  
relationships are maintained. The PLL can be disabled and an  
external clock input provided as the pixel clock. The AD9886  
also offers full sync processing for composite sync and sync-on-  
green applications.  
A
A clamp signal is generated internally or may be provided by the  
user through the CLAMP input pin. This interface is fully pro-  
grammable via a 2-wire serial interface.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  
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