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ACTS280D/SAMPLE PDF预览

ACTS280D/SAMPLE

更新时间： 2024-01-25 18:05:38
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路
页数 文件大小 规格书
3页 107K
描述
ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

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ACTS280D/SAMPLE 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.51其他特性：ODD/EVEN PARITY GENERATOR
系列：ACTJESD-30 代码：R-CDIP-T14
逻辑集成电路类型：PARITY GENERATOR/CHECKER位数：9
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子位置：DUAL

ACTS280D/SAMPLE 数据手册

 浏览型号ACTS280D/SAMPLE的Datasheet PDF文件第2页浏览型号ACTS280D/SAMPLE的Datasheet PDF文件第3页 
TM  
ACTS280MS  
Radiation Hardened 9-Bit Odd/  
Even Parity Generator Checker  
January 1996  
Features  
Pinouts  
14 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR, CDIP2-T14,  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96720 and Intersil’ QM Plan  
LEAD FINISH C  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
I6  
I7  
1
2
3
4
5
6
7
14 VCC  
-10  
• Single Event Upset (SEU) Immunity: <1 x 10  
(Typ)  
Errors/Bit/Day  
13 I5  
12 I4  
11 I3  
10 I2  
NC  
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg  
11  
I8  
• Dose Rate Upset . . . . . . . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
12  
• Dose Rate Survivability. . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
EVEN  
ODD  
GND  
• Latch-Up Free Under Any Conditions  
9
8
I1  
I0  
o
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55 C to +125 C  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
14 PIN CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR, CDFP3-F14  
LEAD FINISH C  
• Input Current ≤ 1µA at VOL, VOH  
TOP VIEW  
• Fast Propagation Delay. . . . . . . . . . . . . . . . 24ns (Max), 16ns (Typ)  
1
2
3
4
5
6
7
14  
13  
12  
I6  
I7  
VCC  
I5  
Description  
The Intersil ACTS280MS is a Radiation Hardened 9-bit odd/even parity  
generator checker device. Both odd and even parity outputs are avail-  
able for generating or checking parity for words up to 9 bits long. Even  
parity is indicated (EVEN output high) when an even number of data  
inputs are high. Odd parity is indicated (ODD output high) when an odd  
number of data inputs are high. Parity checking for larger words can be  
accomplished by tying EVEN output to any input of an additional  
ACTS280MS.  
NC  
I4  
I8  
11  
10  
I3  
EVEN  
ODD  
GND  
I2  
I1  
9
8
I0  
The ACTS280MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACTS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or  
a Ceramic Dual-In-Line Package (D suffix).  
Ordering Information  
PART NUMBER  
5962F9672001VCC  
5962F9672001VXC  
ACTS280D/Sample  
ACTS280K/Sample  
ACTS280HMSR  
TEMPERATURE RANGE  
-55oC to +125oC  
-55oC to +125oC  
25oC  
SCREENING LEVEL  
PACKAGE  
MIL-PRF-38535 Class V  
14 Lead SBDIP  
MIL-PRF-38535 Class V  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
Sample  
Sample  
Die  
25oC  
14 Lead Ceramic Flatpack  
Die  
25oC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518827  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
FN3569.1  
123

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