CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
t
/t
Open
R1 = 500 Ω
R2 = 500 Ω
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
3 V
0 V
1.5 V
1.5 V
Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
Reference
Input
3 V
0 V
1.5 V
CLR
Input
1.5 V
0 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
90%
t
90%
3 V
0 V
1.5 V
10%
1.5 V
10%
1.5 V
CLK
t
r
f
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
Output
Waveform 1
In-Phase
Output
90%
t
≈V
CC
50%
10%
50% V
10%
CC
V
20% V
20% V
CC
S1 at 2 × V
(see Note B)
CC
OL
CC
t
f
r
V
OL
t
t
PLH
PHL
90%
t
t
PHZ
PZH
V
V
OH
90%
Output
Waveform 2
S1 at GND
Out-of-Phase
Output
50% V
10%
50%
10%
CC
V
OH
80% V
80% V
CC
CC
OL
t
t
r
f
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265