Datasheet > ACS8515REV2.1T

ACS8515REV2.1T

更新时间： 2024-01-16 01:32:18

品牌	Logo	应用领域
商升特 - SEMTECH		开关
页数	文件大小	规格书
50页	455K
描述
Line Card Protection Switch for SONET or SDH Network Elements

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技术参数
数据手册

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ACS8515REV2.1T 技术参数

是否Rohs认证：	符合	生命周期：	Not Recommended
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.72	JESD-30 代码：	S-PQFP-G64
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP64,.47SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3,3.3/5 V	认证状态：	Not Qualified
子类别：	Digital Transmission Interfaces	最大压摆率：	190 mA
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

ACS8515REV2.1T 数据手册

ACS8515 Rev2.1 LC/P

FINAL

ADVANCED COMMUNICATIONS

Pin Descriptions

Table 1. Power Pins

SYMBOL

TYPE

NAME/DESCRIPTION

Supply voltage: Digital supply to gates in analog section,

+3.3 Volts. +/- 10%

8, 9, 12

VD+

Supply voltage: Digital supply for differential output pins 19 &

20, +3.3 Volts. +/- 10%

VDD_DIFF

VDD5

VDD5: Digital supply for +5 Volts tolerance to input pins. Connect

to +5 volts (+/- 10%) for clamping to +5 v. Connect to VDD for

clamping to +3.3 v. Leave floating for no clamping, input pins

tolerant up to +5.5 v.

32, 36, 38,

39, 45, 46,

54, 57

VDD

Supply voltage: Digital supply to logic, +3.3 Volts. +/- 10%

Supply voltage: Analog supply to clock multipying APLL, +3.3

Volts. +/- 10%

VA1+

VA2+

Supply voltage: Analog supply to output APLL, +3.3 Volts. +/- 10%

7, 10, 11,

31, 40, 53,

DGND

Supply Ground: Digital ground for logic

Supply Ground: Digital ground for differential output pins 19 &

GND_DIFF

AGND

1, 3, 15

Supply Ground: Analog ground

Table 2. No Connections

SYMBOL

TYPE

NAME/DESCRIPTION

55, 59

Not Connected: Leave to Float

2, 16, 33,

35, 60, 61,

62, 63

Internally Connected: Leave to Float

Internally connected: Leave to Float. Reserved for JTAG control

reset input on next revision

Internally connected: Leave to Float. Reserved for JTAG test mode

select input on next revision

Internally connected: Leave to Float. Reserved for JTAG

boundary scan clock input on next revision

Internally connected: Leave to Float. Reserved for JTAG serial test

data output on next revision

Internally connected: Leave to Float. Reserved for JTAG serial test

data input on next revision

Revision 2.01/December 2005 Semtech Corp.

www.semtech.com

1 2 3 456 7 8...50

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