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ACS20KMSR PDF预览

ACS20KMSR

更新时间: 2024-01-16 19:59:26
品牌 Logo 应用领域
英特矽尔 - INTERSIL 触发器逻辑集成电路
页数 文件大小 规格书
8页 88K
描述
Radiation Hardened Dual 4-Input NAND Gate

ACS20KMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFP包装说明:DFP, FL14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.05
系列:ACJESD-30 代码:R-CDFP-F14
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:2
输入次数:4端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-PRF-38535 Class V
座面最大高度:2.92 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:300k Rad(Si) V
宽度:6.285 mmBase Number Matches:1

ACS20KMSR 数据手册

 浏览型号ACS20KMSR的Datasheet PDF文件第2页浏览型号ACS20KMSR的Datasheet PDF文件第3页浏览型号ACS20KMSR的Datasheet PDF文件第4页浏览型号ACS20KMSR的Datasheet PDF文件第5页浏览型号ACS20KMSR的Datasheet PDF文件第6页浏览型号ACS20KMSR的Datasheet PDF文件第8页 
ACS20MS  
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)  
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE  
c1 LEAD FINISH  
-A-  
-D-  
E
INCHES MILLIMETERS  
MIN  
BASE  
METAL  
(c)  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.785  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
19.94  
7.87  
NOTES  
A
b
-
-
b1  
M
M
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
(b)  
b1  
b2  
b3  
c
3
SECTION A-A  
S
S
S
D
bbb  
C
A - B  
-
D
4
BASE  
PLANE  
S2  
Q
2
A
-C-  
SEATING  
PLANE  
c1  
D
3
L
-
S1  
b2  
eA  
A A  
E
0.220  
5.59  
-
e
0.100 BSC  
2.54 BSC  
-
e
eA/2  
C A - B  
b
C A - B  
c
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
D
aaa  
D
S S  
M
S
S
M
-
NOTES:  
0.125  
0.200  
3.18  
5.08  
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.005  
0.060  
0.38  
0.13  
0.13  
1.52  
5
S1  
S2  
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
o
o
o
o
90  
105  
90  
105  
-
α
aaa  
bbb  
ccc  
M
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
2
8
N
14  
14  
Rev. 0 4/94  
5. Dimension Q shall be measured from the seating plane to the  
base plane.  
6. Measure dimension S1 at all four corners.  
7. Measure dimension S2 from the top of the ceramic body to the  
nearest metallization or lead.  
8. N is the maximum number of terminal positions.  
9. Braze fillets shall be concave.  
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
11. Controlling dimension: INCH.  
Spec Number 518815  
7

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