Datasheet > ACS112D

ACS112D

更新时间： 2024-09-30 04:03:31

品牌	Logo	应用领域
英特矽尔 - INTERSIL		触发器
页数	文件大小	规格书
1页	13K
描述
Radiation Hardened Dual J-K Flip-Flop

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中文翻译

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ACS112D 数据手册

ACS112MS

Radiation Hardened

Dual J-K Flip-Flop

January 1996

Features

Pinouts

16 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835, DESIGNATOR CDIP2-T16,

LEAD FINISH C

• Devices QML Qualiﬁed in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96704 and Intersil’sIntersil QM Plan

TOP VIEW

• 1.25 Micron Radiation Hardened SOS CMOS

CP1

16 VCC

15 R1

14 R2

13 CP2

12 K2

11 J2

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10^-10Errors/Bit/Day

(Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm²/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10¹¹RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability. . . . . . . . . . . >10¹²RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

10 S2

GND

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55^oC to +125^oC

• Signiﬁcant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

16 PIN CERAMIC FLATPACK

MIL-STD-1835, DESIGNATOR CDFP4-F16,

LEAD FINISH C

• Input Logic Levels

TOP VIEW

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

CP1

VCC

• Input Current ≤ 1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)

CP2

Description

The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with

Set and Reset. The output change states on the negative transition of

the clock (CP1N or CP2N).

GND

The ACS112MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of the radiation hard-

ened, high-speed, CMOS/SOS Logic Family.

The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K sufﬁx) or a

Ceramic Dual-In-Line Package (D sufﬁx).

Ordering Information

PART NUMBER

5962F9670401VEC

5962F9670401VXC

ACS112D/Sample

ACS112K/Sample

ACS112HMSR

TEMPERATURE RANGE

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

PACKAGE

-55 C to +125 C

16 Lead SBDIP

-55 C to +125 C

16 Lead Ceramic Flatpack

16 Lead SBDIP

25 C

Sample

16 Lead Ceramic Flatpack

Die

25 C

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Spec Number 518816

File Number 3571.1

中文翻译

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与ACS112D相关器件

型号	品牌	获取价格	描述	数据表
ACS112D/SAMPLE	RENESAS	获取价格	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE
ACS112D/SAMPLE-02	RENESAS	获取价格	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE
ACS112HMSR	INTERSIL	获取价格	Radiation Hardened Dual J-K Flip-Flop
ACS112K	INTERSIL	获取价格	Radiation Hardened Dual J-K Flip-Flop
ACS112K/SAMPLE	RENESAS	获取价格	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAM
ACS112K/SAMPLE-02	RENESAS	获取价格	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CM
ACS112MS	INTERSIL	获取价格	Radiation Hardened Dual J-K Flip-Flop
ACS11D	INTERSIL	获取价格	Radiation Hardened Triple 3-Input AND Gate
ACS11D/SAMPLE-02	RENESAS	获取价格	AC SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14
ACS11D/SAMPLE-03	RENESAS	获取价格	AC SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

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