The power coupled to the cable is a function of the recommended choice since it is further away from
efficiency of the LED, the current applied to the LED the sensitive analogue pins. However, pin 41 is
and the diameter of the fiber optic cable. The larger available for designers if required.
the cable diameter the greater the power coupled.
Digital Mode
The conversion current produced by the receive
diode is a function of the LED efficiency and the
cable diameter. The conversion efficiency is
measured in terms of its ability to convert the
available power to current, known as the
responsivity, given by (A/W). Some examples of link
budgets are given in the Table 1., though note that
significantly better "A" spec. LEDs available, e.g.
from Acapella. “A” spec. LEDs can offer > 12 dB link
budget on 50 µm fiber.
The ACS103 may be used as a controller and data
buffer which allows the device to be used with an
external amplifier and receiver, e.g. for non-fiber
applications. Check with Acapella for details.
Data delay and skew
The data delay in synchronous mode is typically 48
data-bit periods and worst case 100 data-bit periods.
When configured in asynchronous mode the worst
case data delay is 300 µs at 9.216 MHz and 550 µs at
5 MHz. The additional data transmission channels
(XI1/2/3) are delayed by up to 1.2 ms in 'Standard'
mode and up to 2.4 ms in 'Double' mode when used
with a crystal frequency of 9.216 MHz. For other
crystal values the delay changes inversely
proportional to the frequency of operation.
Maximum Link Length
The internal timing chain within the ACS103 limits
the link length to 2.5 km ('Standard' mode) and 5 km
('Double' mode) with a crystal frequency of
9.216 MHz. However, the maximum link length as
determined by the ACS103 timing chain is inversely
proportional to the crystal frequency. Please contact
Acapella if you wish to discuss longer links.
2
The worst case data skews between the main data
channels TxD1/RxD1, TxD2/RxD2 and TxD3/RxD3
across the link are as follows.
TxD inputs
Synchronous : zero data bits.
Asynchronous : 216 * (crystal clock period).
There is a choice of pins for TxD1, pins 12 and 41.
Only one input should be used. The other input will
pull-up to VDD via an internal resistor. Pin 12 is the
1
2
3
4
5
6
7
8
9
DR3
DR1
IC
DM1
RxD1
IC
XO3
IC
NC
VD+ 68
VD+ 67
GND 66
GND 65
DR2 64
TRC 63
DR4 62
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
NC
NC
NC
VG
61
60
59
58
57
56
10 RTS / XI1
11 TxD3
12 TxD1
13 VD+
14 XTI
15 XTO
ACAPELLA
VA+ 55
CON2 54
LDP 53
16 CKC
ACS103
17 TxCL
18 RxCL
19 XI3
20 DM2
21 SEL
22 DM3
23 GND
24 DTR / XI2
25 TxD2
26 ERD
NC
NC
52
51
1-Fiber Modem
LDN 50
CON1 49
CNT 48
GND 47
NC
NC
NC
NC
IC
46
45
44
43
42
27 NC
28 IC
TXD1 41
LIN 40
RSS 39
VD+ 38
VD+ 37
GND 36
GND 35
29 RxD2
30 PORB
31 RxD3
32 CTS / XO1
33 DSR / XO2
34 DCDB
Figure 1. Top view of 68 PLCC package
NC = Not Connected IC = Internally Connected
ACS103 Issue 2.03 May 1996.
6