DTR (Data Terminal Ready) DTE
à
DCE.
RTS (Request to Send) DTE
à
DCE.
CTS (Clear to Send) DCE
à
DTE.
DCDB (Data Carrier Detect) DCE
à
DTE.
or 6.0 kHz using the recommended crystal frequency consequently the jitter on the output RxD. The
- 9.216 MHz. The sample frequency for 'Double' sample frequency is always 1/108 of the chosen
mode is: (crystal freq)/3072, or 3 kHz using the clock frequency in 'Standard' mode and 1/216 in
recommended crystal of 9.216 MHz.
'Double' mode. In ACS101 emulation mode the
sample frequency is 1/36 of crystal clock frequency
in 'Standard' mode and 1/72 of the crystal clock
frequency in 'Double' mode.
The output filters for XO1/2/3 require a minimum
over-sampling of 6 on data presented to the XI1/2/3
inputs.
In ACS101 mode the XI3 input is internally disabled Integrating Capacitor
and the XO3 output is forced into the high impedance
state.
The ACS103 requires the use of an integrating
ceramic capacitor of value 22 nF - 33 nF between
pins CNT and GND for a crystal oscillator frequency
range of 5 - 10 MHz.
RSS High - Modem Handshake Mode.
In modem handshake mode the control signals are
used as conventional handshake signals between the DCDB
DTE (terminal) and the DCE (modem):
The Data Carrier Detect (DCDB) signal goes Low
when the modems are locked and ready for data
transmission.
2
DSR (Data Set Ready) DCE à DTE.
The DCE is powered up and asserts a Low (active
level) on DSR. The DTE is informed that it is PORB
connected to a “live” DCE.
The PORB pin is a single-pin alternative to the reset
combination DM3 = 0, DM2 = 0, DM1 = 1. If left
unconnected the input pulls High to the operational
state. Selecting reset using DM1-DM3 or holding
PORB Low turns off the LED and most of the digital
logic. The device has been designed to power-up
correctly and operate without the aid of PORB.
The DTE is powered up and asserts a Low (active
level) on DTR. The DCE is informed that it is
connected to a “live” DTE. If DTR is set High, the
DCE responds by taking DCDB High.
Transmission Clock TxCL
The DTE recognises that synchronisation has been
achieved (DCDB active) and asserts a Low (active
level) on RTS. This constitutes a request by the DTE
to send data to the far-end modem.
The ACS103 gives a choice between internally and
externally generated transmission clocks (see Figure
2. Timing diagrams for set-up and hold
specifications).
When the CKC pin is held Low, TxCL is configured as
an output producing a clock at the frequency defined
by DR1-DR4. Data is clocked into the device on the
rising edge of the internally supplied clock.
The DCE recognises the active RTS signal and
responds by asserting a Low (active level) on CTS. If
RTS is set High the DCE responds by bringing CTS
High.
When the CKC pin is held High, TxCL is configured
as an input, and will accept an externally produced
transmission clock with a tolerance of up to 500 ppm
with respect to the transmission rate determined by
DR1-DR4. The ACS103 performance is at its best
when external changes on input pins are
synchronised with internal clocks. Therefore,
superior performance is likely when using the
internally generated data transmission clock. If
however, an externally generated transmission clock
is used, then TxCL and TxD are generally
asynchronous to the ACS103 internal clocks,
performance in this case will be enhanced by limiting
the edge speed of the TxCL and TxD signals so that
they are greater than 150 ns. The modem has been
designed to cope with very slow edges on inputs,
without fear of metastability problems.
When synchronisation is achieved between DCEs
the DCDB signal is set Low (active level). If
synchronisation is lost the DCE sets DCDB and CTS
High.
Crystal Clock
A crystal may be connected between the pins XLI and
XLO. Alternatively, XLI may be driven directly by an
external clock. The operational frequency range is
5 MHz to 10 MHz, though communicating devices
must be driven at the same nominal frequency with a
tolerance of 100 ppm. In synchronous mode the
frequency should be 9.216 MHz, resulting in the
standard range of synchronous communication
frequencies selected by DR1-DR4.
Receive Clock RxCL
In synchronous mode data is valid on the rising edge
of RxCL clock (see Figure 2. Timing diagrams). To
ensure that the average receive frequency is the
For asynchronous operation, the choice of crystal
clock frequency dictates the sample rate of the
asynchronous data appearing at the input TxD, and
ACS103 Issue 2.03 May 1996.
3
5秒后页面跳转
VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
ADS1256的资料手册解读、采集电压范围、读数变化原因分析及实际测量遇到的问题
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
