same as the transmitted frequency RxCL is CKC pin is overridden so that TxCL is always
generated from a Digital Phase-Lock Loop (DPLL) configured as an output.
system. The DPLL makes periodic corrections to the
Local Loopback
output RxCL clock to compensate for differences in
the crystal values, and in the case of an externally
supplied transmission clock (TxCL), compensation is
also made for differences in frequency between this
supplied data clock and the selected clock rate (DR1-
DR4). The DPLL is adaptive and will minimise the
frequency of correction and jitter when the crystal
values and transmission clocks are tightly
toleranced.
Local loopback is only available in ACS101
emulation mode.
In local loopback mode data is looped back inside the
near-end modem and is output at its own RxD output.
The data is also sent to the far-end modem;
synchronisation between the modems is maintained.
In local loopback mode, data received from the far-
end device is ignored, except to maintain lock.
When local loopback is activated the DCDB signal
assumes the logic High state. If concurrent requests
occur for local and remote loopback, local loopback
is selected.
If the ACS103 receive FIFO empties (e.g.
transmissions at far-end are halted) the RxCL clock
stops, therefore rising edges of the RxCL clock
always correspond to valid received data bits. This
enables the system designer to use the ACS103 for
the transmission of packets of data with blank periods
between packets. The minimum quanta of data that
can be sent over the link is three bits.
2
When RSS = 0, RTS and DTR are looped back to
CTS and DSR respectively.
Remote Loopback
In asynchronous mode the RxCL clock is turned off.
Remote loopback is only available in ACS101
emulation mode.
Diagnostic/Operational Modes
In remote loopback mode the near-end modem
sends a request to the far-end modem to loopback its
received data, thus returning the data. The far-end
modem also outputs the received data at its RxD.
Both modems are exercised completely, as well as
the LEDs and the fiber optic link. Once remote
loopback is established, DCDB on the near-end
(initiating) modem is Low, and DCDB on the far-end
modem is set High. Any data appearing on the TxD
input of the far-end modem is ignored.
The diagnostic/operational modes input pins DM1-
DM3 may be changed asynchronously within a
window of (crystal clock period) * 1536. The
diagnostic mode signals are sampled 1536 * (crystal
clock period) after a change is detected on any of the
DM inputs. The sampled value is taken as the valid
diagnostic mode.
Diagnostic Mode Lock DM3 DM2 DM1
Full-duplex
Reset
Remote loop-back active
drift
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
When RSS = 0, RTS and DTR are looped back to
CTS and DSR respectively.
Full-duplex
random
drift
active
active
Drift lock
Local loop-back
Full-duplex slave
Full-duplex
Communicating modems attain a stable state where
the "transmit window" of one modem coincides with
the "receive window" of the other allowing for delay
through the optical link. Adjustments to machine
cycles are made automatically during operation to
compensate for differences in crystal frequencies
which cause loss of synchronisation.
Local loopback and remote loop-back are only
available in ACS101 emulation mode.
Full-duplex
In full-duplex configuration the RxCL clock of both
devices tracks the average frequency of the TxCL
clock of the opposing end of the link. The receiving
Digital Phase-Lock Loop (DPLL) system makes
periodic adjustments to the RxCL clock to ensure that
the average frequency is exactly the same as the far-
end TxCL clock. In this mode each TxCL is an
independent master clock and each RxCL a slave
clock.
Using drift lock, synchronisation described above
depends on a difference in the crystal frequencies at
each end of the link, the greater the difference the
faster the locking. Therefore, if the difference
between crystal frequencies is very small (a few
ppm), automatic locking may take tens of seconds.
Active Lock Mode
Active lock mode may be used to accelerate
synchronisation of a pair of communicating modems.
This mode synchronises the modems with less than
250 ms delay, by adjusting the machine cycle of the
modem. Active lock reduces the machine cycle of
the device by 0.5 % ensuring rapid lock. After
Full-duplex slave
In slave mode the TxCL and the RxCL clock is
derived from the TxCL clock of the opposing side of
the link, such that the average frequency is exactly
the same. It is therefore essential that only one
modem is configured in slave mode at a time. The
ACS103 Issue 2.03 May 1996.
4
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