The external reset provides a way to properly reset the ACEx
microcontroller if POR cannot be used in the application. The
external reset pin contains an internal pull-up resistor. Therefore,
to reset the device the reset pin should be held low for at least 2ms
so that the internal clock has enough time to stabilize.
12.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset
setting all I/Os to high-impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is gener-
ated by any one of the following three conditions:
14.0 CLOCK
• Power-on Reset (as described in Section 13.0)
• Brown-out Reset (as described in Section 11.1)
• Watchdog Reset (as described in Section 7.0)
• External Reset18 (as described in Section 13.0)
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a 1MHz
frequency. (See AC Electrical Characteristics.) Upon power-up,
the on-chip oscillator runs continuously unless entering HALT
mode or using an external clock source.
13.0 Power-On-Reset
Ifrequired,anexternaloscillatorcircuitmaybeuseddependingon
the states of the CMODE bits of the initialization register. (See
Table 17) When the device is driven using an external clock, the
clock input to the device (G1/CKI) can range between DC to
4MHz. For external crystal configuration, the output clock (CKO)
is on the G0 pin. (See Figure 28) If an external crystal or RC is
used, internally the input frequency (CKI) is divided-down by four
to yield the corresponding instruction clock. If the device is
configured for an external square clock, it will not be divided.
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
wasdesignedtorespondtofastlowtohightransitionsbetween0V
and VCC. The circuit will not work if VCC does not drop to 0V before
thenextpower-upsequence. Inapplicationswhere1)the VCC rise
is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the
nextpower-upsequencetheexternalresetoptionshouldbeused.
Table 17: CMODEx Bit Definition
CMODE[1]
CMODE[0]
Clock Type
Internal 1 MHz clock
0
0
1
1
0
1
0
1
External square clock
External crystal/resonator
External RC clock
Figure 27: BOR and POR Circuit Relationship Diagram
V
(Pin 8)
CC
BOR
output
V
CC
V
CC
1.75
0
V
CC
0
Reset
circuit
output
Global Reset
to Logic
Time
BOR Output
A
POR
output
External
Reset
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
Pin
V
CC
(14-Pin Only)
5.0V
1.8V
0
(Pin 7)
V
CC
POR Output
Pulse
POR
output
0
18 Available only on the 14-pin package option.
www.fairchildsemi.com
29
ACE1101 Product Family Rev. B.2