Datasheet > ACE1101BVN14

ACE1101BVN14

更新时间： 2022-01-18 22:30:00

品牌	Logo	应用领域
其他 - ETC		微控制器
页数	文件大小	规格书
35页	2055K
描述
8-Bit Microcontroller

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ACE1101BVN14 数据手册

Figure 28: Crystal (a) and RC (b) Oscillator Diagrams

CKI

(G1)

CKO

(G0)

CKI

(G1)

CKO

(G0)

33pF

15.0 HALT Mode

16.0 IDLE Mode

The HALT mode is a power saving feature that almost completely

shuts down the device for current conservation. The device is

placed into HALT mode by setting the HALT enable bit (EHALT)

of the HALT register through software using only the “LD M, #”

instruction. EHALT is a write only bit and is automatically cleared

upon exiting HALT. When entering HALT, the internal oscillator

and all the on-chip systems including the LBD and the BOR

circuits are shut down.

In addition to the HALT mode power saving feature, the device

also supports an IDLE mode operation. The device is placed into

IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT

EIDLE is a write only bit and is automatically cleared upon exiting

IDLE. The IDLE mode operation is similar to HALT except the

internal oscillator, the Watchdog, and the Timer 0 remain active

while the other on-chip systems including the LBD and the BOR

circuits are shut down.

The device can exit HALT mode only by the MIW circuit. There-

fore, prior to entering HALT mode, software must configure the

MIW circuit accordingly. (See Section 8) After a wakeup from

HALT, a 1ms start-up delay is initiated to allow the internal

oscillator to stabilize before normal execution resumes. Immedi-

ately after exiting HALT, software must clear the Power Mode

Clear (PMC) register by only using the “LD M, #” instruction. (See

Figure 30)

The device can exit IDLE by a Timer 0 overflow every 8192 cycles

or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior

to entering, software must configure the MIW circuit accordingly.

(See Section 8) Once a wake from IDLE mode is triggered, the

core will begin normal operation by the next clock cycle. Immedi-

ately after exiting IDLE mode, software must clear the Power

Mode Clear (PMC) register by using only the “LD M, #” instruction.

(See Figure 31)

Figure 29: HALT Register Definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

undefined

EIDLE

EHALT

Figure 30: Recommended HALT Flow

Figure 31: Recommended IDLE Flow

Normal Mode

HALT, #01H

LD HALT, #01h

Timer0

Underflow

IDLE Mode

Multi-Input

Wakeup

Multi-Input

Halt

Wakeup

LD PMC, #00H

Resume Normal

Mode

LD PMC, #00h

Resume

Normal Mode

www.fairchildsemi.com

ACE1101 Product Family Rev. B.2

1...27 28 293031 32 33...35

下载PDF

与ACE1101BVN14相关器件

型号	品牌	描述	获取价格	数据表
ACE1101E	FAIRCHILD	Arithmetic Controller Engine (ACEx⑩) for Low	获取价格
ACE1101EMT8	FAIRCHILD	Arithmetic Controller Engine (ACEx⑩) for Low	获取价格
ACE1101EMT8X	FAIRCHILD	Arithmetic Controller Engine (ACEx⑩) for Low	获取价格
ACE1101EMX	FAIRCHILD	Microcontroller, 8-Bit, EEPROM, 1MHz, CMOS, PDSO14, SOIC-14	获取价格
ACE1101EN	ETC	8-Bit Microcontroller	获取价格
ACE1101EN14	ETC	8-Bit Microcontroller	获取价格