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ACE1101BN

更新时间： 2024-02-19 02:48:48
品牌 Logo 应用领域
其他 - ETC 微控制器
页数 文件大小 规格书
35页 2055K
描述
8-Bit Microcontroller

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ACE1101BN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP-8
针数：8Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.82
具有ADC：NO地址总线宽度：
位大小：8CPU系列：ACE1101
最大时钟频率：4 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
长度：9.817 mmI/O 线路数量：6
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/5 V认证状态：Not Qualified
RAM（字节）：64ROM（单词）：1024
ROM可编程性：EEPROM座面最大高度：5.08 mm
速度：1 MHz子类别：Microcontrollers
最大压摆率：5.5 mA最大供电电压：5.5 V
最小供电电压：2.2 V标称供电电压：2.7 V
表面贴装：NO技术：CMOS
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

ACE1101BN 数据手册

 浏览型号ACE1101BN的Datasheet PDF文件第27页浏览型号ACE1101BN的Datasheet PDF文件第28页浏览型号ACE1101BN的Datasheet PDF文件第29页浏览型号ACE1101BN的Datasheet PDF文件第31页浏览型号ACE1101BN的Datasheet PDF文件第32页浏览型号ACE1101BN的Datasheet PDF文件第33页 
Figure 28: Crystal (a) and RC (b) Oscillator Diagrams  
a)  
b)  
CKI  
(G1)  
CKO  
(G0)  
CKI  
(G1)  
CKO  
(G0)  
1M  
R
V
CC  
C
33pF  
33pF  
15.0 HALT Mode  
16.0 IDLE Mode  
The HALT mode is a power saving feature that almost completely  
shuts down the device for current conservation. The device is  
placed into HALT mode by setting the HALT enable bit (EHALT)  
of the HALT register through software using only the “LD M, #”  
instruction. EHALT is a write only bit and is automatically cleared  
upon exiting HALT. When entering HALT, the internal oscillator  
and all the on-chip systems including the LBD and the BOR  
circuits are shut down.  
In addition to the HALT mode power saving feature, the device  
also supports an IDLE mode operation. The device is placed into  
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT  
register through software using only the “LD M, #” instruction.  
EIDLE is a write only bit and is automatically cleared upon exiting  
IDLE. The IDLE mode operation is similar to HALT except the  
internal oscillator, the Watchdog, and the Timer 0 remain active  
while the other on-chip systems including the LBD and the BOR  
circuits are shut down.  
The device can exit HALT mode only by the MIW circuit. There-  
fore, prior to entering HALT mode, software must configure the  
MIW circuit accordingly. (See Section 8) After a wakeup from  
HALT, a 1ms start-up delay is initiated to allow the internal  
oscillator to stabilize before normal execution resumes. Immedi-  
ately after exiting HALT, software must clear the Power Mode  
Clear (PMC) register by only using the “LD M, #” instruction. (See  
Figure 30)  
The device can exit IDLE by a Timer 0 overflow every 8192 cycles  
or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior  
to entering, software must configure the MIW circuit accordingly.  
(See Section 8) Once a wake from IDLE mode is triggered, the  
core will begin normal operation by the next clock cycle. Immedi-  
ately after exiting IDLE mode, software must clear the Power  
Mode Clear (PMC) register by using only the “LD M, #” instruction.  
(See Figure 31)  
Figure 29: HALT Register Definition  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
undefined  
undefined  
undefined  
undefined  
undefined  
undefined  
EIDLE  
EHALT  
Figure 30: Recommended HALT Flow  
Figure 31: Recommended IDLE Flow  
Normal Mode  
Normal Mode  
LD  
HALT, #01H  
LD HALT, #01h  
Timer0  
Underflow  
IDLE Mode  
Multi-Input  
Wakeup  
Multi-Input  
Halt  
Wakeup  
LD PMC, #00H  
Resume Normal  
Mode  
LD PMC, #00h  
Resume  
Normal Mode  
www.fairchildsemi.com  
30  
ACE1101 Product Family Rev. B.2  
1...27282930313233...35

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