Datasheet > ACD2206

ACD2206

更新时间： 2022-11-25 10:40:39

品牌	Logo	应用领域
ANADIGICS		电视有线电视
页数	文件大小	规格书
20页	459K
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CATV/TV/VIDEO DOWNCONVERTER WITH DUAL SYNTHESIZER

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ACD2206 数据手册

ACD2206

LOGIC PROGRAMMING

Synthesizer Register Programming

The ACD2206 includes two PLL synthesizers. Each

synthesizer contains programmable Reference and

Main dividers, which allow a wide range of local

oscillator frequencies. The 22-bit registers that control

the dividers are programmed via a shared three-wire

bus, consisting of Data, Clock and Enable lines.

Table 7: Register Select Bits

SELECT

BITS

DESTINATION REGISTER FOR

SERIAL DATA

The data word for each register is entered serially

in order with the most significant bit (MSB) first and

the least significant bit (LSB) last. The rising edge

of the Clock pulse shifts each data value into the

of the data entry, then set high to latch the data into

the register. (See Figure 4.)

Reference Divider Register for PLL2

Main Divider Register for PLL2

Reference Divider Register for PLL1

Main Divider Register for PLL1

Reference Divider Programming

The reference divider register for each synthesizer

consists of fifteen divider bits, five program mode

bits and the two register select bits, as shown in

Table 8. The fifteen divider bits allow a divide ratio

from 3 to 32767, inclusive, as shown in Table 9.

The two least significant bits of each register are

programmed during a particular data entry cycle.

Table 7 indicates the register select bit settings used

to program each of the available registers.

Table 8: Reference Divider Registers

22 21 20 19 18 17 16 15 14 13 12 11 10

Program Mode Reference Divider Divide Ratio, R

MSB

LSB

Select

15 14 13 12 11 10

Table 9: Reference Divider R Counter Bits

DIVIDE

RATIO R

15 14 13 12 11 10

32767

Notes:

Divide ratios less than 3 are prohibited.

PRELIMINARY DATA SHEET - Rev 1.0

10/2003

1...5 6 789 10 11...20

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