7.1.2.6 Windower/IZ (WIZ) Stage ..........................................................76
Video Engine.....................................................................................................77
2D Engine.........................................................................................................77
7.3.1 Chipset VGA Registers.............................................................................77
7.3.2 Logical 128-Bit Fixed BLT and 256 Fill Engine .............................................77
7.2
7.3
8
Display Interfaces....................................................................................................78
8.1
GMCH Display Overview .....................................................................................78
8.1.1 Display Planes........................................................................................78
8.1.1.1 Planes A and B..........................................................................79
8.1.1.2 Sprite A and B ..........................................................................79
8.1.1.3 Cursors A and B........................................................................79
8.1.1.4 VGA ........................................................................................79
8.1.2 Display Pipes..........................................................................................79
8.1.3 DisplayPorts...........................................................................................79
Analog DisplayPorts ...........................................................................................80
8.2.1 CRT ......................................................................................................80
8.2.1.1 Integrated DAC.........................................................................80
8.2.1.2 Sync Signals.............................................................................80
8.2.2 TV ........................................................................................................80
Digital DisplayPorts............................................................................................81
8.3.1 LVDS ....................................................................................................81
8.3.1.1 LVDS Pair States.......................................................................82
8.3.1.2 Single-Channel versus Dual-Channel Mode ...................................82
8.3.1.3 Panel Power Sequencing.............................................................82
8.3.1.4 LVDS DDC................................................................................83
8.3.2 iHDMI ...................................................................................................83
8.3.2.1 HDCP.......................................................................................84
8.3.3 DisplayPort (DP).....................................................................................84
8.3.3.1 DP Aux Channel ........................................................................85
8.3.3.2 DP Hot-Plug Detect (HPD) ..........................................................85
8.3.4 SDVO....................................................................................................85
8.3.4.1 SDVO Control Bus .....................................................................86
Co-Existence of DisplayPorts ...............................................................................86
8.2
8.3
8.4
9
Power Management and Sequencing........................................................................88
9.1
Power Management Features...............................................................................88
9.1.1 Dynamic Power Management on I/O..........................................................88
9.1.1.1 Host........................................................................................88
9.1.1.2 System Memory........................................................................88
9.1.1.3 PCI Express..............................................................................88
9.1.1.4 DMI.........................................................................................88
9.1.1.5 Intel Management Engine...........................................................88
9.1.2 System Memory Power Management .........................................................89
9.1.2.1 Disabling Unused System Memory Outputs ...................................89
9.1.2.2 Dynamic Power Management of Memory.......................................89
9.1.2.3 Conditional Self-Refresh.............................................................89
ACPI States Supported .......................................................................................90
9.2.1 System .................................................................................................90
9.2.2 Processor ..............................................................................................90
9.2.3 Internal Graphics Display Device Control....................................................90
9.2.4 Internal Graphics Adapter........................................................................91
Interface Power States Supported........................................................................91
9.3.1 PCI Express Link States...........................................................................91
9.3.2 Main Memory States................................................................................91
Chipset State Combinations ................................................................................92
9.4.1 CPU Sleep (H_CPUSLP#) Signal Definition..................................................93
9.2
9.3
9.4
6
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