2.2.1 Memory Channel A Interface ....................................................................27
2.2.2 Memory Channel B Interface ....................................................................28
2.2.3 Memory Reference and Compensation .......................................................29
PCI Express-Based Graphics Interface Signals .......................................................30
2.3.1 DisplayPort (DP), iHDMI and SDVO on PCI Express Based Graphics ...............30
DMI – GMCH to ICH Serial Interface.....................................................................30
Integrated Graphics Interface Signals...................................................................31
2.5.1 CRT DAC Signals ....................................................................................31
2.5.2 Analog TV-out Signals .............................................................................31
2.5.3 LVDS Signals .........................................................................................32
2.5.4 Display Data Channel (DDC) and GMBUS Support .......................................33
Intel® High Definition Audio (Intel® HD Audio) Signals ..........................................33
Intel® Management Engine Interface
2.3
2.4
2.5
2.6
2.7
(Intel® MEI) Signals ..........................................................................................34
PLL Signals .......................................................................................................34
Reset and Miscellaneous Signals ..........................................................................35
2.8
2.9
2.10 Non-Critical to Function (NCTF) ...........................................................................36
2.11 Power and Ground .............................................................................................36
3
Host Interface..........................................................................................................39
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
FSB Source Synchronous Transfers ......................................................................39
FSB IOQ Depth..................................................................................................39
FSB OOQ Depth.................................................................................................39
FSB AGTL+ Termination .....................................................................................39
FSB Dynamic Bus Inversion.................................................................................39
FSB Interrupt Overview ......................................................................................40
APIC Cluster Mode Support .................................................................................40
FSB Dynamic Frequency Switching.......................................................................40
4
System Address Map................................................................................................41
4.1
Legacy Address Range........................................................................................44
4.1.1 MS-DOS Range (0000_0000h – 0009_FFFFh) .............................................45
4.1.2 Legacy Video Area (000A_0000h to 000B_FFFFh)........................................45
4.1.2.1 Compatible SMRAM Address Range (000A_0000h to 000B_FFFFh) ...45
4.1.2.2 Monochrome Adapter (MDA) Range (000B_0000h to 000B_7FFFh)...45
4.1.3 Expansion Area (000C_0000h to 000D_FFFFh) ...........................................45
4.1.4 Extended System BIOS Area (000E_0000h to 000E_FFFFh)..........................46
4.1.5 System BIOS Area (000F_0000h to 000F_FFFFh)........................................46
4.1.6 Programmable Attribute Map (PAM) Memory Area Details.............................47
Main Memory Address Range (1 MB to TOLUD) ......................................................47
4.2.1 ISA Hole (15 MB to 16 MB) ......................................................................48
4.2.2 TSEG ....................................................................................................48
4.2.3 DPR (DMA Protected Range).....................................................................48
4.2.4 Pre-allocated Memory..............................................................................48
PCI Memory Address Range (TOLUD to 4 GB)........................................................49
4.3.1 APIC Configuration Space (FEC0_0000h to FECF_FFFFh) ..............................51
4.3.2 HSEG (FEDA_0000h to FEDB_FFFFh).........................................................51
4.3.3 FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF) .............................51
4.3.4 High BIOS Area ......................................................................................51
Main Memory Address Space (4 GB to TOUUD) ......................................................52
4.4.1 Memory Remap Background.....................................................................52
4.4.2 Memory Remapping (or Reclaiming)..........................................................53
PCI Express Configuration Address Space..............................................................53
4.5.1 PCI Express Graphics Attach ....................................................................53
4.5.2 Graphics Aperture...................................................................................53
Graphics Memory Address Ranges........................................................................54
4.2
4.3
4.4
4.5
4.6
4
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