Datasheet > ABB0302XC

ABB0302XC

更新时间： 2022-02-26 12:16:43

品牌	Logo	应用领域
ABRACON		PC 动态存储器双倍数据速率
页数	文件大小	规格书
6页	63K
描述
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

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ABB0302XC 数据手册

ABB0302

DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

I2C BUS CONFIGURATION SETTING

R/W

Address Assignment

Slave

Receiver/Transmitter

Provides both slave write and readback functionality

Data Transfer Rate

Standard mode at 100kbits/s

This serial protocol is designed to allow both blocks write and read from the controller. The

bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred

must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will

terminate the transfer. The write or read block both begins with the master sending a slave

address and a write condition (0xD2) or a read condition (0xD3).

Data Protocol

Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte

Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte

Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at

power-up is = (0x09).

I2C CONTROL REGISTERS

1. BYTE 6: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Enhanced DDR Drive. 1 = Enhanced 25%

Reserved

45, 44

43, 42

39, 38

34, 33

DDR11T, DDR11C

DDR10T, DDR10C

DDR9T, DDR9C

DDR8T, DDR8C

2. BYTE 7: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

30, 29

28, 27

21, 22

19, 20

15, 16

10, 11

6, 7

DDR7T, DDR7C

DDR6T, DDR6C

DDR5T, DDR5C

DDR4T, DDR4C

DDR3T, DDR3C

DDR2T, DDR2C

DDR1T, DDR1C

DDR0T, DDR0C

4, 5

30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 3

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