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AB28F400B5B80

更新时间： 2023-12-18 00:00:00
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
44页 344K
描述
5 VOLT BOOT BLOCK FLASH MEMORY

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中文翻译

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AB28F400B5B80 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：0.525 X 1.110 INCH, PLASTIC, SOP-44针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.76
最长访问时间：80 ns其他特性：MIN 100K EXTENDED BLOCK ERASE CYCLES; CAN BE CONFG AS 125KX16; BOTTOM BOOT BLOCK
启动块：BOTTOMJESD-30 代码：R-PDSO-G44
长度：28.2 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1端子数量：44
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：512KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL编程电压：5 V
认证状态：Not Qualified座面最大高度：2.95 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL类型：NOR TYPE
宽度：13.3 mmBase Number Matches：1

AB28F400B5B80 数据手册

 浏览型号AB28F400B5B80的Datasheet PDF文件第4页浏览型号AB28F400B5B80的Datasheet PDF文件第5页浏览型号AB28F400B5B80的Datasheet PDF文件第6页浏览型号AB28F400B5B80的Datasheet PDF文件第8页浏览型号AB28F400B5B80的Datasheet PDF文件第9页浏览型号AB28F400B5B80的Datasheet PDF文件第10页 
E
28F200B5, 28F004/400B5, 28F800B5  
Table 2. Pin Descriptions  
Name and Function  
Symbol  
Type  
ADDRESS INPUTS for memory addresses. Addresses are internally latched  
during a write cycle.  
A0–A18  
INPUT  
28F200: A[0–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]  
A9  
INPUT  
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During  
this mode, A0 decodes between the manufacturer and device IDs. When BYTE#  
is at a logic low, only the lower byte of the signatures are read. DQ15/A–1 is a  
don’t care in the signature mode when BYTE# is low.  
DQ0–DQ7  
INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle  
OUTPUT during a Program command. Inputs commands to the Command User Interface  
when CE# and WE# are active. Data is internally latched during the write cycle.  
Outputs array, intelligent identifier and status register data. The data pins float to  
tri-state when the chip is de-selected or the outputs are disabled.  
DQ8–DQ15  
INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle  
OUTPUT during a Program command. Data is internally latched during the write cycle.  
Outputs array data. The data pins float to tri-state when the chip is de-selected or  
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide  
mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7.  
Not applicable to 28F004B5.  
CE#  
INPUT  
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and  
sense amplifiers. CE# is active low. CE# high de-selects the memory device and  
reduces power consumption to standby levels. If CE# and RP# are high, but not  
at a CMOS high level, the standby current will increase due to current flow  
through the CE# and RP# input stages.  
OE#  
WE#  
INPUT  
INPUT  
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during  
a read cycle. OE# is active low.  
WRITE ENABLE: Controls writes to the command register and array blocks. WE#  
is active low. Addresses and data are latched on the rising edge of the WE#  
pulse.  
RP#  
INPUT  
RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to  
control two different functions: reset/deep power-down mode and boot block  
unlocking. It is backwards-compatible with the BX/BL/BV products.  
When RP# is at logic low, the device is in reset/deep power-down mode,  
which puts the outputs at High-Z, resets the Write State Machine, and draws  
minimum current.  
When RP# is at logic high, the device is in standard operation. When RP#  
transitions from logic-low to logic-high, the device defaults to the read array mode.  
When RP# is at VHH, the boot block is unlocked and can be programmed or  
erased. This overrides any control from the WP# input.  
7
PRELIMINARY  
1...45678910...44

中文翻译

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AB28F400B5B80 替代型号

型号 品牌 替代类型 描述 数据表
TMS28F400AFB80BDBJQ TI

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