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AB28F200BX-T90 PDF预览

AB28F200BX-T90

更新时间: 2024-01-06 19:32:40
品牌 Logo 应用领域
英特尔 - INTEL 闪存内存集成电路光电二极管
页数 文件大小 规格书
33页 459K
描述
2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY

AB28F200BX-T90 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:1.110 X 0.525 INCH, PLASTIC, SOP-44针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.77
Is Samacsys:N最长访问时间:90 ns
其他特性:TOP BOOT BLOCK备用内存宽度:8
启动块:TOP命令用户界面:YES
数据轮询:NOJESD-30 代码:R-PDSO-G44
长度:28.2 mm内存密度:2097152 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1部门数/规模:1,2,1,1
端子数量:44字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:128KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP44,.63封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V编程电压:12 V
认证状态:Not Qualified座面最大高度:2.95 mm
部门规模:16K,8K,96K,128K最大待机电流:0.00008 A
子类别:Flash Memories最大压摆率:0.065 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:MOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL切换位:NO
类型:NOR TYPE宽度:13.3 mm
Base Number Matches:1

AB28F200BX-T90 数据手册

 浏览型号AB28F200BX-T90的Datasheet PDF文件第1页浏览型号AB28F200BX-T90的Datasheet PDF文件第2页浏览型号AB28F200BX-T90的Datasheet PDF文件第4页浏览型号AB28F200BX-T90的Datasheet PDF文件第5页浏览型号AB28F200BX-T90的Datasheet PDF文件第6页浏览型号AB28F200BX-T90的Datasheet PDF文件第7页 
A28F200BX-T/B  
Program and Erase Automation allows program  
and erase operations to be executed using a two-  
write command sequence to the CUI. The internal  
Write State Machine (WSM) automatically executes  
the algorithms and timings necessary for program  
and erase operations, including verifications, there-  
by unburdening the microprocessor or microcontrol-  
ler. Writing of memory data is performed in word or  
byte increments for the A28F200BX family typically  
within 9 ms which is a 100% improvement over pre-  
vious flash memory products.  
1.0 PRODUCT FAMILY OVERVIEW  
Throughout this datasheet the A28F200BX refers to  
both the A28F200BX-T and A28F200BX-B devices.  
Section 1 provides an overview of the 2-Mbit flash  
memory family including applications, pinouts and  
pin descriptions. Section 2 describes in detail the  
specific memory organization. Section 3 provides a  
description of the family’s principles of operation. Fi-  
nally, the family’s operating specifications are de-  
scribed.  
The Status Register (SR) indicates the status of the  
WSM and whether the WSM successfully completed  
the desired program or erase operation.  
1.1 Main Features  
The A28F200BX boot block flash memory family is a  
very high performance 2-Mbit (2,097,152 bit) memo-  
ry family organized as either 128-KWords (131,072  
words) of 16 bits each or 256-Kbytes (262,144  
bytes) of 8 bits each.  
Maximum Access Time of 90 ns (TACC) is achieved  
b
over the automotive temperature range ( 40 C to  
supply voltage range and 100 pF  
§
125 C), 10% V  
§
CC  
output load.  
I maximum Program current is 40 mA for x16  
PP  
Five Separately Erasable Blocks including a hard-  
ware-lockable boot block (16,384 Bytes), two pa-  
rameter blocks (8,192 Bytes each) and two main  
blocks (1 block of 98,304 Bytes and 1 block of  
131,072 Bytes) are included on the 2-Mbit family. An  
erase operation erases one of the main blocks in  
typically 3 seconds, and the boot or parameter  
blocks in typically 1.5 seconds. Each block can be  
independently erased and programmed 1,000 times.  
operation and 30 mA for x8 operation. I Erase  
PP  
current is 30 mA maximum. V erase and pro-  
PP  
gramming voltage is 11.4V to 12.6V (V  
g
Active Current of 25 mA is achieved.  
e
5%) under all operating conditions. Typical I  
12V  
PP  
CC  
The 2-Mbit boot block flash family is also designed  
with an Automatic Power Savings (APS) feature to  
minimize system battery current drain and allow for  
very low power designs. Once the device is ac-  
cessed to read array data, APS mode will immedi-  
ately put the memory in static mode of operation  
The Boot Block is located at either the top  
(A28F200BX-T) or the bottom (A28F200BX-B) of the  
address map in order to accommodate different mi-  
croprocessor protocols for boot code location. The  
hardware lockable boot block provides the most  
secure code storage. The boot block is intended to  
store the kernel code required for booting-up a sys-  
where I  
next read is initiated.  
active current is typically 1 mA until the  
CC  
Ý
Ý
When the CE and RP pins are at V  
BYTE pin is at either V  
and the  
or GND the CMOS  
CC  
Ý
tem. When the RP pin is between 11.4V and 12.6V  
the boot block is unlocked and program and erase  
Ý
CC  
Standby mode is enabled where I  
80 mA.  
is typically  
CC  
Ý
operations can be performed. When the RP pin is  
at or below 6.5V the boot block is locked and pro-  
gram and erase operations to the boot block are  
ignored.  
A Deep Power-Down Mode is enabled when the  
Ý
RP pin is at ground minimizing power consumption  
and providing write protection during power-up con-  
The A28F200BX products are available in the ROM/  
EPROM compatible pinout and housed in the  
44-Lead PSOP (Plastic Small Outline) package as  
shown in Figure 3.  
ditions. I  
current during deep power-down mode  
CC  
is 50 mA typical. An initial maximum access time or  
Reset Time of 300 ns is required from RP switch-  
ing until outputs are valid. Equivalently, the device  
has a maximum wake-up time of 210 ns until writes  
to the Command User Interface are recognized.  
Ý
The Command User Interface (CUI) serves as the  
interface between the microprocessor or microcon-  
troller and the internal operation of the A28F200BX  
flash memory.  
3

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