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AB-557-03 PDF预览

AB-557-03

更新时间: 2024-10-03 12:51:31
品牌 Logo 应用领域
ABRACON 晶体时钟发生器输出元件PC
页数 文件大小 规格书
7页 3845K
描述
CRYSTAL-LESS PCI EXPRESS DUAL OUTPUT ULTRA MINIATURE PURE SILICONTM SMD CLOCK GENERATOR

AB-557-03 数据手册

 浏览型号AB-557-03的Datasheet PDF文件第2页浏览型号AB-557-03的Datasheet PDF文件第3页浏览型号AB-557-03的Datasheet PDF文件第4页浏览型号AB-557-03的Datasheet PDF文件第5页浏览型号AB-557-03的Datasheet PDF文件第6页浏览型号AB-557-03的Datasheet PDF文件第7页 
CRYSTAL-LESS PCI EXPRESS DUAL OUTPUT ULTRA MINIATURE  
PURE SILICONTM SMD CLOCK GENERATOR  
Moisture Sensitivity Level  
MSL 1 – 14 QFN  
MSL 3 – 16 TSSOP  
AB-557-03 Series  
3.2 x 2.5 x 0.85 mm (14 Pin QFN)  
5.1 x 4.5 x 1.1 mm (16 Pin TSSOP)  
RoHS  
Pb  
Compliant  
FEATURES:  
APPLICATIONS:  
• Solid State Storage  
• Storage Area Networks  
• Passive Optical Networks  
• Ethernet: 1G, 10GBASE-T/KR/LR/SR, and FCoE  
• TV and other Consumer Electronics  
• Industrial and Medical  
• Meets PCIe Gen1, Gen2, & Gen3 specs.  
• High Performance MEMS Technology by Discera  
• Available Mixed Output Formats: HCSL, LVPECL, LVDS or LVCMOS  
• Wide Temperature Range: -40° to 105° C  
• Wide Supply Range: 2.25V to 3.6 V  
• Low Power Consumption  
• Scanner, Printer  
• Excellent Shock & Vibration Immunity  
STANDARD SPECIFICATIONS:  
Parameters  
Minimum  
2.3  
Typical  
Maximum Unite  
Notes  
Frequency  
f0  
100  
460*1  
+70  
MHz  
°C  
Operating Temperature  
Storage Temperature  
Overall Freq. Stability*2  
Supply Voltage  
-20  
-55  
-50  
+2.25  
See options  
+150  
+50  
+3.6  
°C  
Δf  
VDD  
ppm See options  
V
RL=50,  
F01=F02=100.00MHz  
Supply Current- Enabled  
IDD  
60  
21  
mA  
Supply Current- Disabled  
Startup Time  
Enable Time  
IDD  
tsu  
tEN  
tDA  
23  
5
20  
5
mA  
ms  
ns  
Disable Time  
ns  
"1" (VIH≥0.75*Vdd) or Open: Oscillation  
"0" (VIL<0.25*Vdd) : Hi Z  
40kΩ pull-up resistor  
embedded  
Tri-state Function (Standby/Disable)  
V
Aging  
-5.0  
+5.0  
ppm First year  
VOH  
Output Offset Voltage  
VOL  
0.725  
V
RL=50 Ω  
0.10  
Peak to Peak Output Swing  
Rise Time  
Fall Time  
Duty Cycle  
Period Jitter  
750  
mV  
ps  
ps  
%
psRMS  
psRMS  
Single-Ended  
RL=50 , CL=2pF  
(20% to 80%)*VDD  
Differential  
F01=F02=100.00MHz  
tr  
tf  
200  
200  
48  
400  
400  
52  
SYM  
JPER  
RJ  
DJ  
TJ  
2.5  
0.540  
0.832  
8.536  
PCIe Gen 1.1  
TJ= DJ + 14.069 x RJ  
(BER 10-12)  
41.9  
86.0  
psp-p  
Integrated Phase Noise  
(Common Clock  
Architecture)  
PCIe Gen 2.1  
1.5 MHz to Nyquist  
PCIe Gen 2.1  
10kHz to 1.5 MHz  
JRMS-CCHF  
0.458  
3.1  
psRMS  
JRMS-CCLF  
JRMS-CC  
0.030  
0.165  
0.561  
3.0  
1.0  
4.0  
psRMS PCIe Gen 3.0  
PCIe Gen 2.1  
JRMS-DCHF  
1.5 MHz to Nyquist  
PCIe Gen 2.1  
10kHz to 1.5 MHz  
PCIe Gen 3.0  
psRMS  
Integrated Phase Noise  
(Data Clock Architecture)  
JRMS-DCLF  
JRMS-DC  
1.778  
0.147  
7.5  
1.0  
psRMS  
*1. For frequency other than 100MHz, please contact ABRACON or consider using ASEMDxx series  
2. Frequency stability includes frequency variations due to initial tolerance, temp. and power supply voltage  
Visit www.abracon.com for Terms & Conditions of Sale  
Revised: 10.31.12  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001| www.abracon.com  
ABRACON IS  
ISO9001:2008  
CERTIFIED  

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