Datasheet > AAT3242ITP-QO-T1

AAT3242ITP-QO-T1

更新时间： 2024-01-01 07:27:49

品牌	Logo	应用领域
ANALOGICTECH		稳压器
页数	文件大小	规格书
16页	227K
描述
300mA/150mA Dual CMOS LDO Linear Regulator

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技术参数
数据手册

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AAT3242ITP-QO-T1 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.84	湿度敏感等级：	1

AAT3242ITP-QO-T1 数据手册

AAT3242

300mA/150mA Dual CMOS LDO Linear Regulator

Pin Descriptions

Pin #

Symbol

Function

ENA

Enable Regulator A pin; this pin should not be left floating. When pulled

low, the PMOS pass transistor turns off and the device enters shutdown

mode, consuming less than 1µA.

2, 3, 8, 9

GND

Ground connection pins.

POKA

Power OK pin with open drain output. It is pulled low when the OUTA pin is

below the 10% regulation window.

OUTB

INB

Low current (150mA) regulator output pin; should be decoupled with a

2.2µF or greater output low-ESR ceramic capacitor.

Input voltage pin for Regulator B; should be decoupled with 1µF or greater

capacitor.

ENB

Enable Regulator B; this pin should not be left floating. When pulled low, the

PMOS pass transistor turns off and the device enters shutdown mode, con-

suming less than 1µA.

POKB

OUTA

INA

Power OK pin with open drain output. It is pulled low when the OUTB pin is

below the 10% regulation window.

High-current (300mA) regulator output pin; should be decoupled with a

2.2µF or greater output low-ESR ceramic capacitor.

Input voltage pin for Regulator A; should be decoupled with 1µF or greater

capacitor.

Pin Configuration

TSOPJW-12

(Top View)

ENA

GND

POKA

OUTB

INB

INA

OUTA

POKB

GND

ENB

3242.2005.01.1.4

123 4 5 6 7...16

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