Datasheet > AAT3218IGV-2.7-T1

AAT3218IGV-2.7-T1

更新时间： 2024-02-05 22:07:30

品牌	Logo	应用领域
ANALOGICTECH		/
页数	文件大小	规格书
18页	368K
描述
150mA MicroPower⑩ High Performance LDO

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AAT3218IGV-2.7-T1 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.84	湿度敏感等级：	3
Base Number Matches：	1

AAT3218IGV-2.7-T1 数据手册

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AAT3218

150mA MicroPower™ High Performance LDO

The power dissipation for a 150mA load occurring

(C_IN, C_OUT, and C_BYP), and the load circuit are all

connected to a common ground plane. This type of

layout will work in simple applications where good

power supply ripple rejection and low self noise are

not a design concern. For high-performance appli-

cations, this method is not recommended.

for 8.2% of the duty cycle will be 21mW. Finally,

the two power dissipation levels can summed to

determine the total true power dissipation under

the varied load:

P_D(total)= P_D(100mA)+ P_D(150mA)

P_D(total)= 156.6mW + 21mW

P_D(total)= 177.6mW

The problem with the layout in Figure 1 is the

bypass capacitor and output capacitor share the

same ground path to the LDO regulator ground pin,

along with the high-current return path from the

load back to the power supply. The bypass capac-

itor node is connected directly to the LDO regulator

internal reference, making this node very sensitive

to noise or ripple. The internal reference output is

fed into the error amplifier, thus any noise or ripple

from the bypass capacitor will be subsequently

amplified by the gain of the error amplifier. This

effect can increase noise seen on the LDO regula-

tor output, as well as reduce the maximum possi-

ble power supply ripple rejection. There is PCB

trace impedance between the bypass capacitor

connection to ground and the LDO regulator

ground connection. When the high load current

returns through this path, a small ripple voltage is

created, feeding into the C_BYPloop.

The maximum power dissipation for the AAT3218

operating at an ambient temperature of 85°C is

211mW. The device in this example will have a total

power dissipation of 177.6mW. This is well within

the thermal limits for safe operation of the device.

Printed Circuit Board Layout

Recommendations

In order to obtain the maximum performance from

the AAT3218 LDO regulator, careful consideration

should be given to the printed circuit board (PCB)

layout. If grounding connections are not properly

made, power supply ripple rejection, low output self

noise, and transient response can be compromised.

Figure 1 shows a common LDO regulator layout

scheme. The LDO regulator, external capacitors

I_LOAD

I_IN

VIN

VOUT

BYP

V_IN

LDO

Regulator

GND

I_GND

DC INPUT

C_BYP

C_OUT

R_LOAD

C_IN

C_BYP

GND

LOOP

I_RIPPLE

I_BYP+ noise

GND

R_TRACE

I_LOADreturn + noise and ripple

Figure 1: Common LDO Regulator Layout with C_BYPRipple Feedback Loop.

Figure 2 shows the preferred method for the bypass

bypass and output capacitor directly to the LDO reg-

ulator ground pin. This method will eliminate any

load noise or ripple current feedback through the

LDO regulator.

and output capacitor connections. For low output

noise and highest possible power supply ripple

rejection performance, it is critical to connect the

3218.2006.04.1.8

1...11 12 131415 16 17 18

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