Datasheet > AAT3215IGV-2.6-T1

AAT3215IGV-2.6-T1

更新时间： 2024-02-11 04:45:22

品牌	Logo	应用领域
ANALOGICTECH		/
页数	文件大小	规格书
18页	343K
描述
150mA CMOS High Performance LDO

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数据手册

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AAT3215IGV-2.6-T1 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.57	湿度敏感等级：	3
Base Number Matches：	1

AAT3215IGV-2.6-T1 数据手册

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AAT3215

150mA CMOS High Performance LDO

Figure 2 shows the preferred method for the bypass

and output capacitor connections. For low output

noise and highest possible power supply ripple

rejection performance, it is critical to connect the

bypass and output capacitor directly to the LDO reg-

ulator ground pin. This method will eliminate any

load noise or ripple current feedback through the

LDO regulator.

Evaluation Board Layout

The AAT3215 evaluation layout follows the recom-

mend printed circuit board layout procedures and

can be used as an example for good application

layouts (see Figures 3, 4, and 5).

Note: Board layout shown is not to scale.

I_LOAD

I_IN

V_IN

V_OUT

V_IN

LDO

Regulator

BYP

GND

I_GND

DC INPUT

C_BYP

C_OUT

R_LOAD

C_IN

C_BYP

I_RIPPLE

I_BYP+ noise

GND

LOOP

GND

R_TRACE

I_LOADreturn + noise and ripple

Figure 1: Common LDO Regulator Layout with C_BYPRipple Feedback Loop.

I_LOAD

I_IN

V_IN

V_OUT

BYP

V_IN

DC INPUT

GND

LDO

Regulator

GND

I_GND

C_BYP

C_OUT

R_LOAD

C_IN

I_BYPonly

I_RIPPLE

R_TRACE

I_LOADreturn + noise and ripple

Figure 2: Recommended LDO Regulator Layout.

3215.2006.05.1.6

1...11 12 131415 16 17 18

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