Wide Input Voltage, Fault Tolerant, Independently Controlled
Multi-Channel LED Driver with I2C interface
A8517
PINOUT DIAGRAM AND TERMINAL LIST TABLE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GATE
INS
SW
1
2
OVP
VIN
PGND
ADDR
SCL
3
EN
4
FSET/SYNC
COMP
AGND
VDD
5
SDA
6
PAD
GOP1
GPO2
LED10
LED9
LED8
LED7
LED6
AGND
7
8
FLAG
LED1
9
10
11
12
13
14
LED2
LED3
LED4
LED5
Package LP, 28-Pin TSSOP Pinout Diagram
Terminal List Table
Name
Number
Function
This pin has 4 levels that allow the user to set up to 4 physical IC addresses based on the voltage level. Connect a
resistor to GND to set the voltage level.
ADDR
25
Analog ground; connect all noise-sensitive components (especially for COMP) to this quiet ground, and connect to
thermal pad.
AGND
COMP
EN
7, 15
Output of error amplifier and compensation node; connect a type-2 feedback network from this pin to AGND for
control loop compensation.
6
4
9
5
1
Enable for the A8517; IC stays in shutdown mode as long as EN = VEN(L), enables the part when connected to VEN(H)
or to VIN.
This active-low, open-drain pin is used to indicate that system attention is required, such as during startup or a fault
condition. Connect a resistor with a value from 10 to 100 kΩ between this pin and the target logic level voltage.
¯¯¯¯¯¯¯¯
FLAG
Frequency/synchronization pin; a resistor, RFSET, from this pin to GND sets the switching frequency, and this pin can
also be used to synchronize to an external switching frequency.
FSET/SYNC
GATE
Gate driver for optional external PMOS input disconnect switch, that in the event of a fault (such as output shorted to
GND) is turned off by this pin being pulled high (turning off input supply); if not used, this pin should be left open.
GPO1
GPO2
22
21
General purpose open-drain output 1, programmable by internal register.
General purpose open-drain output 2, programmable by internal register.
Input current sense, used together with VIN pin to detect input overcurrent fault; if not used, this pin should be tied to
VIN.
INS
LEDx
OVP
2
10, 11, 12,
13, 14, 16,
17, 18, 19, 20
LED current sink channels 1 through 10. Up to 60 mA per channel. Any unused LEDx pin should be connected to
GND through a 4.7 kΩ resistor.
Connect this pin to output voltage VOUT to provide output Overvoltage Protection (OVP) and Undervoltage Protection
(UVP).
27
–
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 8 vias, directly in the pad, and AGND and PGND pins must be connected to this
ground pad on the PCB.
PAD
Power ground for internal NMOS switching device; connect this pin to ground terminal of output ceramic capacitor(s)
and to thermal pad.
PGND
26
SCL
SDA
SW
24
23
28
8
I2C clock signal.
I2C data signal.
The drain of the internal NMOS switch of the boost converter.
Output of internal LDO; connect a 0.47 µF decoupling capacitor between this pin and AGND.
Input power to the A8517.
VDD
VIN
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
