Datasheet > A81407

A81407

更新时间： 2022-06-24 15:42:25

品牌	Logo	应用领域
急速微 - ALLEGRO		/
页数	文件大小	规格书
58页	3082K
描述
Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator

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A81407 数据手册

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Terminal List Table

Number

Name

VCP

Function

Charge pump reservoir capacitor connection, for phase disconnects

Charge pump reservoir capacitor connection, for buck/boost regulator

Input voltage pin

VCP

VCP2

VIN

38 CP2C2

37 CP2C1

36 LX

VCP2

VIN

GND

VCC

ENB

Ground

GND

VCC

ENB

POE

NPOR

FFn

35 CP1

Internal voltage regulator bypass capacitor pin

Logic enable input from a microcontroller or DSP

Gate drive enable, latches low to put the system into a safe state

34 CP2

33 PGND

32 LG

POE

NPOR

Active-low, open-drain VUC fault detection output. Using SPI

programming, Watchdog (WD) fault and/or V5A can be added to the

NPOR logic.

31 VREG

30 VUC

29 V5A

FFn

ENBAT

GVBB

SVBB

Fault Flag to the microcontroller, open-drain, active low

Ignition enable input from the key/switch via a series resistor

Battery line MOSFET gate drive

ENBAT 10

GVBB

PAD

–

28 WD_Fn

27 COMP

26 AMUXO

25 WD_IN

24 MOSI

23 MISO

22 CS

SVBB 12

GW 13

Battery line MOSFET source reference

W phase MOSFET gate drive

W phase MOSFET source reference

GV 15

SV 16

V phase MOSFET gate drive

V phase MOSFET source reference

GU 17

SU 18

U phase MOSFET gate drive

21 SCK

U phase MOSFET source reference

V5P2 19

20 V5P1

V5P2

V5P1

SCK

5 V protected regulator output

Package LV, 38-Pin eTSSOP

Pinout Diagram

SPI clock input from the microcontroller

SPI Chip Select input from the microcontroller

SPI data output to the microcontroller (Master Input, Slave Output)

SPI data input from the microcontroller (Master Output, Slave Input)

Watchdog refresh input from a microcontroller or DSP

MISO

MOSI

WDIN

AMUXO Analog Multiplexer output

COMP

WD_Fn

V5A

Error amplifier compensation network pin for the buck/boost pre-regulator

Open-drain, WD fault output. Latches low if a WD fault is detected.

5 V regulator output

VUC

3.3 V regulator output (or 5V for A81407-1)

Voltage feedback input of the pre-regulator and input to the LDOs

Boost gate drive output for the buck/boost pre-regulator

Power ground

VREG

PGND

CP2

Charge pump capacitor connection

CP1

Charge pump capacitor connection

Switching node for the buck/boost pre-regulator

Charge pump capacitor connection

CP2C1

CP2C2

PAD

Charge pump capacitor connection

Exposed thermal pad

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

1...3 4 567 8 9...58

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