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A64S9316

更新时间： 2022-11-26 00:35:04

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A64S9316 数据手册

A64S9316

Avoid Timing

Following figures are show you an abnormal timing which

is not supported on Super RAM and their solution.

At normal operation, if your system have a timing which

sustain invalid states over 10ms at normal mode like

Figure 1. There are some guide line for proper operation

of Super RAM.

When your system have multiple invalid address signal

shorter than tRC on the timing which showed in Figure 1,

Super RAM need toggle the CE1 to “high” about “tRC”

(Figure 2).

Over 10us

CE1

Less than t ^RC

Address

Figure 1

toggle CE1 to high every 10us

10us

70ns

CE1

Address

Figure 2

PRELIMINARY

(July, 2002, Version 0.1)

AMIC Technology, Inc.

1...4 5 678 9 10...15

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型号	品牌	描述	获取价格	数据表
A64S9316G-70	AMICC	512K X 16 Bit Low Voltage Super RAM	获取价格
A64S9316G-70I	AMICC	512K X 16 Bit Low Voltage Super RAM	获取价格
A64S9316G-85	AMICC	512K X 16 Bit Low Voltage Super RAM	获取价格
A64S9316G-85I	AMICC	512K X 16 Bit Low Voltage Super RAM	获取价格
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