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A6282 PDF预览

A6282

更新时间: 2024-01-28 00:12:12
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
13页 441K
描述
16-Channel Constant-Current LED Driver

A6282 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LEAD FREE, MS-013AD, SOIC-24
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
数据输入模式:SERIAL接口集成电路类型:LED DISPLAY DRIVER
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:15.4 mm湿度敏感等级:3
复用显示功能:NO功能数量:1
区段数:16端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3/5 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Display Drivers最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
最小 fmax:30 MHzBase Number Matches:1

A6282 数据手册

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16-Channel Constant-Current LED Driver  
A6282  
Functional Description  
The maximum channel output current can be calculated as:  
Normal Operation  
Serial data present at the SDI (Serial Data In) input is transferred  
to the shift register on the transition from logic 0 to logic 1 of the  
CLK (Clock) input pulse. On succeeding CLK pulses, the register  
shifts data towards the SDO (Serial Data Out) output. The serial  
data must appear at the input prior to the rising edge of the CLK  
waveform.  
IO(max) = (18483.1/ REXT) + 0.67 , for VDD = 3.0 to 3.6 V ,  
or  
IO(max) = (18841.2/ REXT) + 0.68 , for VDD = 4.5 to 5.5 V ,  
where REXT is the value of the user-selected external resistor,  
which should not be less than 374 Ω.  
A chart of the maximum per channel (OUT0 to OUT15) constant  
Data present in any register is transferred to the respective latch  
when the LE (Latch Enable) input is high (serial-to-parallel con-  
version). The latches continue to accept new data as long as LE is  
held high (level triggered).  
output current, IO(max), at various values of REXT is shown in  
,
the Operating Characteristics section.  
Undervoltage Lockout  
The A6282 includes an internal undervoltage lockout (UVLO)  
circuit that disables the outputs in the event that the logic supply  
voltage drops below a minimum acceptable level. This feature  
prevents the display of erroneous information, a necessary func-  
tion for some critical applications. Upon recovery of the logic  
supply voltage after a UVLO event, all internal shift registers and  
latches are set to 0. The A6282 is then in normal mode.  
Applications where the latches are bypassed (LE tied high)  
¯¯¯¯  
require that the OE (Output Enable) input be high during serial  
¯¯¯¯  
data entry. When OE is high, the output sink drivers are disabled  
(off). The data stored in the latches is not affected by the state  
¯¯¯¯  
¯¯¯¯  
of OE. With OE active (low), the outputs are controlled by the  
state of their respective latches.  
Thermal Shutdown Protection  
If the junction temperature exceeds the threshold temperature,  
TJTSD, 165°C typical, the outputs will be turned off until the junc-  
tion temperature cools down through the thermal shutdown hys-  
teresis, 15°C typical. The shift register and output latches register  
will remain active during a thermal shutdown event. Therefore,  
there is no need to reset the data in the output latches.  
Setting Maximum Channel Current  
The maximum output current per channel is set by a single exter-  
nal resistor, REXT, which is placed between the REXT pin and  
GND. The voltage on REXT, VEXT, is set by an internal band gap  
and is 1.21 V, typical.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
9
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  

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