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A6275EA-T PDF预览

A6275EA-T

更新时间: 2024-02-28 01:55:45
品牌 Logo 应用领域
急速微 - ALLEGRO 显示驱动器驱动程序和接口接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
12页 533K
描述
8-Bit Serial Input Constant-Current Latched LED Driver

A6275EA-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LEAD FREE, MS-013AA, SOIC-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:COMMON-ANODE
数据输入模式:SERIAL显示模式:SEGMENT
接口集成电路类型:LED DISPLAY DRIVERJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.3 mm
湿度敏感等级:3复用显示功能:NO
功能数量:1区段数:8
端子数量:16最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Display Drivers最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:BICMOS
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mm最小 fmax:10 MHz

A6275EA-T 数据手册

 浏览型号A6275EA-T的Datasheet PDF文件第4页浏览型号A6275EA-T的Datasheet PDF文件第5页浏览型号A6275EA-T的Datasheet PDF文件第6页浏览型号A6275EA-T的Datasheet PDF文件第8页浏览型号A6275EA-T的Datasheet PDF文件第9页浏览型号A6275EA-T的Datasheet PDF文件第10页 
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
TIMING REQUIREMENTS and SPECIFICATIONS  
(Logic Levels are VDD and Ground)  
C
50%  
B
CLOCK  
A
SERIAL  
DATA IN  
DATA  
50%  
t
p
SERIAL  
DATA OUT  
50%  
DATA  
D
E
LATCH  
ENABLE  
50%  
OUTPUT  
ENABLE  
LOW = ALL OUTPUTS ENABLED  
t
p
HIGH = OUTPUT OFF  
50%  
DATA  
LOW = OUTPUT ON  
Dwg. WP-029-1  
OUT  
N
A. Data Active Time Before Clock Pulse  
(Data Set-Up Time), tsu(D) ............................. 50 ns  
B. Data Active Time After Clock Pulse  
(Data Hold Time), th(D) ................................. 20 ns  
C. Clock Pulse Width, tw(CK) .................................. 50 ns  
D. Time Between Clock Activation  
and Latch Enable, tsu(L) ............................... 100 ns  
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns  
F. Output Enable Pulse Width, tw(OE) ................... 4.5 s  
HIGH = ALL OUTPUTS DISABLED (BLANKED)  
50%  
OUTPUT  
ENABLE  
t
F
pLH  
t
t
r
f
90%  
50%  
10%  
OUT  
N
DATA  
t
pHL  
NOTE: Timing is representative of a 10 MHz clock. Sig-  
nificantly higher speeds are attainable.  
Dwg. WP-030-1A  
Max. Clock Transition Time, tr or tf ....................... 10 s  
Serial data present at the input is transferred to the shift  
register on the logic 0-to-logic 1 transition of the CLOCK input  
pulse. On succeeding CLOCK pulses, the registers shift data in-  
formation towards the SERIAL DATA OUTPUT. The serial data  
must appear at the input prior to the rising edge of the CLOCK  
input waveform.  
Information present at any register is transferred to the  
respective latch when the LATCH ENABLE is high (serial-to-  
parallel conversion). The latches continue to accept new data as  
long as the LATCH ENABLE is held high. Applications where  
the latches are bypassed (LATCH ENABLE tied high) will  
require that the OUTPUT ENABLE input be high during serial  
data entry.  
When the OUTPUT ENABLE input is high, the output sink  
drivers are disabled (OFF). The information stored in the latches  
is not affected by the OUTPUT ENABLE input. With the OUT-  
PUT ENABLE input low, the outputs are controlled by the state  
of their respective latches.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
6
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  

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